Seagate Technology Incorporated

Lsi Corporation

International Business Machines Corporation

Netapp, Inc.

Lsi Logic Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Mylex Corporation

Mohamad H El-Batal

Jon David Trantham

Praveen Viraraghavan

John West Dykes

Darshana H Mehta

Ian James Gilbert

Matthew J Totin

Sangita Shreedharan Kalarickal

Bret S Weber

Jason M Stuhlsatz

John R Kloeppner

Thomas E Richardson

John Michael Bent

Dennis E Gates

Robert E Stubbs

Macen Shinsato

Mark Nossokoff

Brian Dennis McKean

William Patrick Delaney

Timothy E Hoglund

Charles E Nichols

Ujjwal Lanjewar

Zahirudeen Premji

William G Deitz

Mark Ish

Ian Davies

David Alan Burton

Rodney A Dekoning

Noel Simen Otterness

William A Brant

Stephen B Johnson

Keith W Holt

Michael David Barrell

Kevin Lee Van Pelt

Russell J Henry

Ray M Jantz

Krishnakumar Rao Surugucchi

Randolph Wesley Sterns

Anant Baderdinni

Jeremy D Stover

Matthew B Lovell

Yoshihiro Fujie

Phillip Raymond Colline

Randy Kay Hall

Alan Lee Stewart

David Jerome Allen

John V Sherman

Richard O Weiss

Jeffrey S Werning

Bikrant Kumar Singh

Dennis Kleppen

Greg Shogan

Thomas Sing-Klat Liong

David Copeland

Sai Narasimhamurthy

John Dietterich

Brian Mckean

Jeff Werning

The technology disclosed herein provides a memory blade including a plurality of fabric switches configured to receive commands from a plurality of host clients, an address decoder and tracker circuit communicatively connected to the fabric switches and configured to determine the source of commands received at the fabric switches an aggregator crossbar configured to provide bandwidth aggregation between host clients and a plurality of memory modules; and a buffer module configured to couple the commands from the plurality of host clients with the plurality of memory modules.

Fault-tolerant memory appliance

Method and apparatus for managing a front-end cache formed of ferroelectric memory element (FME) cells. Prior to storage of writeback data associated with a pending write command from a client device, an intelligent cache manager circuit forwards a first status value indicative that sufficient capacity is available in the front-end cache for the writeback data. Non-requested speculative readback data previously transferred to the front-end cache from the main NVM memory store may be jettisoned to accommodate the writeback data. A second status value may be supplied to the client device if insufficient capacity is available to store the writeback data in the front-end cache, and a different, non-FME based cache may be used in such case. Mode select inputs can be supplied by the client device specify a particular quality of service level for the front-end cache, enabling selection of suitable writeback and speculative readback data processing strategies.

Intelligent management of ferroelectric memory in a data storage device

Apparatus and method for managing data in a non-volatile memory (NVM) having an array of ferroelectric memory cells (FMEs). A data set received from an external client device is programmed to a group of the FMEs at a target location in the NVM using a selected profile. The selected profile provides different program characteristics, such as applied voltage magnitude and pulse duration, to achieve desired levels of power used during the program operation, endurance of the data set, and latency effects associated with a subsequent read operation to retrieve the data set. The profile may be selected from among a plurality of profiles for different operational conditions. The ferroelectric NVM may form a portion of a solid-state drive (SSD) storage device. Different types of FMEs may be utilized including ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs).

Balancing power, endurance and latency in a ferroelectric memory

A system on chip (SOC) integrated circuit device having an incorporated ferroelectric memory configured to be selectively refreshed, or not, depending on different operational modes. The ferroelectric memory is formed of an array of ferroelectric memory elements (FMEs) characterized as non-volatile, read-destructive semiconductor memory cells each having at least one ferroelectric layer. The FMEs can include FeRAM, FeFET or FTJ constructions. A read/write circuit writes data to the FMEs and subsequently reads back data from the FMEs responsive to respective write and read signals supplied by a processor circuit of the SOC. A refresh circuit is selectively enabled in a first normal mode to refresh the FMEs after a read operation, and is selectively disabled in a second exception mode so that the FMEs are not refreshed after a read operation. The FMEs can be used as a main memory, a cache, a buffer, an OTP, a keystore, etc.

System on chip (SOC) with processor and integrated ferroelectric memory

A data storage system can utilize one or more data storage devices that employ a solid-state non-volatile read destructive memory consisting of ferroelectric memory cells. A leveling strategy can be generated by a wear module connected to the memory with the leveling strategy prescribing a plurality of memory cell operating parameters associated with different amounts of cell wear. The wear module may monitor activity of a memory cell and detect an amount of wear in the memory cell as a result of the monitored activity, which can prompt changing a default set of operating parameters for the memory cell to a first stage of operating parameters, as prescribed by the leveling strategy, in response to the detected amount of wear.

Read destructive memory wear leveling system

A non-volatile memory (NVM) is formed of memory cells each having multiple ferroelectric memory elements (FMEs). Each FME stores data in relation to an electrical polarity of a recording layer formed of ferroelectric or anti-ferroelectric material. Each multi-FME memory cell is coupled to a set of external control lines activated by a control circuit in a selected order to perform program and/or read operations upon the FMEs. The FMEs may share a nominally identical construction or may have different constructions. Data are programmed and written responsive to the respective program/read responses of the FMEs. Constructions can include ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs). The NVM may form a portion of a data storage device, such as a solid-state drive (SSD).

Non-volatile memory cell with multiple ferroelectric memory elements (FMEs)

Apparatus and method for managing data in a processing system, such as but not limited to a data storage device such as a solid-state drive (SSD). A ferroelectric stack register memory has a first arrangement of ferroelectric memory cells (FMEs) of a first construction and a second arrangement of FMEs of a different, second construction arranged to provide respective cache lines for use by a controller, such as a programmable processor. A pointer mechanism is configured to provide pointers to point to each of the respective cache lines based on a time sequence of operation of the processor. Data sets can be migrated to the different arrangements by the controller as required based on the different operational characteristics of the respective FME constructions. The FMEs may be non-volatile and read-destructive. Refresh circuitry can be selectively enacted under different operational modes.

Stack register having different ferroelectric memory element constructions

A memory device formed of ferroelectric field effect transistors (FeFETs). The memory device can be used as a front end buffer, such as in a data storage device having a non-volatile memory (NVM). A controller can be configured to transfer user data between the NVM and an external client (host) via the buffer. The FeFETs can be arranged in a two-dimensional (2D) or a three-dimensional (3D) array. A monitor circuit can be used to monitor operation of the FeFETs. An optimization controller can be used to adjust at least one operational parameter associated with the FeFETs responsive to the monitored operation by the monitor circuit. The FeFETs may require a refresh operation after each read operation. A power down sequence can involve a read operation without a subsequent refresh operation to wipe the FeFETs, the read operation jettisoning the data read from the buffer memory.

Front end buffer having ferroelectric field effect transistor (FeFET) based memory

A data storage system can employ a read destructive memory configured to fill a first cache with a first data set from a data repository prior to populating a second cache with a second data set describing the first data set with the first and second cache each having non-volatile ferroelectric memory cells. An entirety of the first cache may be read in response to a cache hit in the second cache with the cache hit responsive to a data read command from a host and with the first cache being read without a refresh operation restoring the data of the first cache.

Intelligent cache with read destructive memory cells

A data storage system can employ a read destructive memory configured with multiple levels. A non-volatile memory unit can be programmed with a first logical state in response to a first write voltage of a first hysteresis loop by a write controller prior to being programmed to a second logical state in response to a second write voltage of the first hysteresis loop, as directed by the write controller. The first and second logical states may be present concurrently in the non-volatile memory unit and subsequently read concurrently as the first logical state and the second logical state.

Data storage with multi-level read destructive memory

A data storage system can have one or more hosts connected to a data storage subsystem with the host having a host processor and the data storage subsystem having a controller. Write back data generated at the host triggers the host processor to allocate a cache location in the data storage subsystem where the generated data is subsequently stored. The generated write back data is written in a non-volatile destination address as directed by the controller prior to waiting for a secondary event with the generated data stored in both the cache location and the non-volatile destination address. Detection of the secondary event prompts the controller to signal the host processor that the cache location is free for new data.

Data storage system with write back cache

A method includes receiving a piece of data for storage in a storage system, breaking the piece of data into a plurality of fixed size data portions, and determining a deduplication hash for each of the fixed size data portions. The method further includes checking for matching hashes already stored in the storage system, storing fixed size data portions unmatched to an already stored hash with metadata identifying the unmatched hash fixed size data portions in the storage system, and storing metadata for hash fixed size data portions already stored in the data storage system. The piece of data is reviewed for further deduplication using sliding window hashes during background activity of the data storage system.

Hybrid deduplication in storage systems

Operations are monitored that involve a plurality of servers coupled to a plurality of data storage enclosures via a rack-level, storage networking fabric. The servers are operable to provide data storage services utilizing the data storage enclosures via a network. The data storage enclosures each have one or more data storage devices. The servers and the data storage enclosures are mounted within a data center rack. A failed unit determined that includes a failed one of the servers or a failed one of the data storage devices within a selected one of the data storage enclosures. A replacement is found for the failed unit within the data center rack, and the replacement is established for the failed unit within the data center rack. The establishment of the replacement involves establishing a new connection via the storage networking fabric.

Data center storage availability architecture using rack-level network fabric

A system includes an enclosure having an air inlet end and an air outlet end, air movers positioned near the air outlet end, a first data connector positioned near the air outlet end between the air movers, a heat-generating electrical component positioned immediately between the data connector and the air inlet end, a first heat sink positioned immediately between at least one of the air movers and the air inlet end, and a first conductive pipe thermally coupled between the heat-generating electrical component and the first heat sink.

Heat sink and printed circuit board arrangements for data storage systems

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Boulder, CO, United States of America

Mohamad H El-Batal