Stmicroelectronics S.a.

Mohamad Chehadi

David Naura

Bertrand Bertrand

Jean Devin

Christophe Mani

A procedure is provided for identifying an operating mode of a device, such as an EEPROM memory that communicates according to a communication protocol, such as 'IC' (Inter Integrated Circuit). The signal is an 'ACK' or &#x201c;ACKNOWLEDGE&#x201d; signal. At least one operating mode of a device is identified by a time lag from the time the signal (ACK) is transmitted relative to the time foreseen by the protocol for the signal. This approach can be used to verify that the test mode commands (read or write) have been taken into account correctly.

Procedure and device for identifying an operating mode of a controlled device

A method is provided for erasing or programming at least one memory cell of a non-volatile memory. According to the method, a state fixation pulse is applied to a floating gate transistor of the memory cell. The state fixation pulse also includes, successively, a portion at a reference voltage, and a state fixation portion at a voltage with sufficient amplitude for the transfer of electrons between the drain and the gate of the floating gate transistor. Additionally, an external adjustment signal is applied to the memory to adjust the state fixation portion to a predetermined duration, and the state fixation portion is adjusted to the predetermined duration in real time as a function of the state of the adjustment signal. Also provided is a non-volatile memory.

Method for erasing/programming a non-volatile electrically erasable memory

An electrically programmable and erasable memory includes memory cells connected to word lines and to bit lines arranged in columns. Bit lines selection transistors are driven by bit lines selection signals. Column selection latches each includes a locking element for a column selection signal and a circuit for delivering a gate control signal which depends on the output of the locking element. Each column selection latch delivers, in addition to a gate control signal, a bit lines selection signal. This signal depends on the output of the locking element at least during programming and reading phases of the memory cells.

Word programmable EEPROM memory comprising column selection latches with two functions

A circuit produces a voltage for the erasure or programming of a memory cell. The circuit includes a capacitor, and a discharge circuit connected to a first terminal of the capacitor. The discharge circuit includes a first transistor, a drain of which is connected to the first terminal of the capacitor. The first transistor activates the discharge circuit when a discharge signal is received by a gate of the first transistor. The discharge circuit includes a slow discharge arm and a fast discharge arm parallel-connected to the source of the first transistor. The discharge circuit produces a low discharge current or a high discharge current for discharging the capacitor as a function of an operating mode selection signal.

Circuit and associated method for the erasure or programming of a memory cell

The integrated circuit includes a detection circuit and a rectifier circuit that are series-connected, to provide a rectified voltage, and a low voltage regulation circuit that receives the rectified voltage and provides a low voltage. According to the invention, the circuit also has a voltage production circuit that receives the rectified voltage and produces a high voltage different from the low voltage. In one embodiment, the circuit also includes a memory having a memory array receiving the low voltage and the high voltage.

Voltage production circuit

In a memory integrated circuit comprising an internal circuit for the generation of a programming high voltage and comprising a first pad designed to receive a main logic supply voltage below five volts, a second specific supply pad is designed to supply the high voltage generation circuit. This enables the by application of a specific logic supply voltage with a voltage level greater than that of the main logic supply voltage in test mode or in application mode.

Methods of operating an integrated circuit with memory having an internal circuit for the generation of a programming high voltage

An integrated circuit card receives power in the form of a radio frequency signal and includes a voltage generator that produces a first power supply voltage. The card also includes a voltage booster circuit for producing a high voltage that receives the first power supply voltage at a first supply input terminal. The voltage booster circuit also receives a second power supply voltage higher than the first power supply voltage at a second supply input terminal.

Charge pump type voltage booster circuit

A secured electrically modifiable non-volatile memory includes a circuit to determine if memory cells therein have been exposed to ultraviolet radiation. The memory includes at least one additional memory cell, called a reference cell, and an associated read circuit for detecting any erasure of the reference cell by ultraviolet radiation. At each access to the memory, the reference cell is read by the associated read circuit. If the state of the reference cell is different from its initial electrical state, then operation of the memory is stopped.

Secured EEPROM memory comprising means for the detection of erasure by ultraviolet radiation

In a memory integrated circuit comprising an internal circuit for the generation of a programming high voltage and comprising a first pad designed to receive a main logic supply voltage below five volts, a second specific supply pad is designed to supply the high voltage generation circuit. This enables the application of a specific logic supply voltage with a voltage level greater than that of the main logic supply voltage in test mode or in application mode.

Integrated circuit with memory comprising an internal circuit for the

An electrically erasable and programmable non-volatile semiconductor memory includes memory registers that are addressable individually or by blocks. The memory also has a protection register in which a protection word can be written. The protection word has a given number of bits that encode a boundary address of the memory register or a block of memory registers. The boundary address divides the memory space into an upper zone and a lower zone. The protection word also has a zone bit whose value determines which of the two zones of the memory is to be write protectable.

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Aix en Provence, France

Mohamad Chehadi