Sima Technologies, Inc.

Intel Corporation

Moenes Zaher Iskarous

Nishit Harshad Shah

Srivathsa Dhruvanarayan

Kavitha Prasad

Reed Kotler

Yogesh Laxmikant Chobe

Spenser Don Gilliland

Sedny S J Attia

Sorin Iacobovici

Bradley L Taylor

Paul M Stillwell, Jr

A system-on-chip (SoC) integrated circuit product includes a machine learning accelerator (MLA). It also includes other processor cores, such as general purpose processors and application-specific processors. It also includes a network-on-chip for communication between the different modules. The SoC implements a heterogeneous compute environment because the processor cores are customized for different purposes and typically will use different instruction sets. Applications may use some or all of the functionalities offered by the processor cores, and the processor cores may be programmed into different pipelines to perform different tasks.

Heterogeneous computing on a system-on-chip, including machine learning inference

A compiler receives a description of a machine learning network and generates a computer program that implements the machine learning network. The computer program includes statically scheduled instructions that are executed by a mesh of processing elements (Tiles). The instructions executed by the Tiles are statically scheduled because the compiler can determine which instructions are executed by which Tiles at what times. For example, for the statically scheduled instructions, there are no conditions, branching or data dependencies that can be resolved only at run-time, and which would affect the timing and order of the execution of the instructions.

Machine learning network implemented by statically scheduled instructions, with system-on-chip

Machine learning network implemented by statically scheduled instructions, with MLA chip

Machine learning network implemented by statically scheduled instructions, with compiler

A method and apparatus for saving and restoring architectural states utilizing hardware is described. A first portion of an architectural state of a processing element, such as a core, is concurrently saved upon being updated. A remaining portion of the architectural state is saved to memory in response to a save state triggering event, which may include a hardware event or a software event. Once saved, the state is potentially transferred to another processing element, such as a second core. As a result, hardware, software, or combination thereof may transfer architectural states between multiple processing elements, such as threads or cores, of a processor utilizing hardware support.

Saving and restoring architectural state for processor cores

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San Jose, CA, United States of America

Moenes Zaher Iskarous