Micron Technology Incorporated

Moeha Shibuya

Kenichi Watanabe

Kumiko Ishii

Kazuyuki Morishige

Toshiaki Tsukihashi

Yuki Miura

Saaya Izumi

An apparatus that includes first, second, third and fourth circuit regions arranged in a first direction in numerical order. The first circuit region includes a first global power supply line extending in a second direction vertical to the first direction and a first local power supply line, the first local power supply line being branched from the first global power supply line and extending in the first direction across the second, third and fourth regions. The third circuit region includes a first power switch coupled between the first local power supply line and an internal power supply line extending in the first direction across the first, second, third and fourth regions. Each of the second and fourth regions includes a circuit coupled to the first local power supply line and an additional circuit coupled to the internal power supply line.

Semiconductor device capable of switching operation voltage

Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.

Output buffer circuit with metal option

Apparatuses with a signal line in a semiconductor device are described. An example apparatus includes one or more power supply voltage lines in a first conductive layer, a plurality of transistors and a signal line in a second conductive layer. Each transistor of the plurality of transistors includes an active region disposed in a substrate and a gate electrode above the active region. The signal line in the second conductive layer is below the first conductive layer and above the active regions of the plurality of transistors. The signal line is coupled to the gate electrodes of the plurality of transistors. The signal line has electrical resistance higher than electrical resistance of the power supply voltage line.

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Sagamihara, Japan

Moeha Shibuya