Lsi Corporation

Avago Technologies General IP (Singapore) Pte. Ltd.

Moby J Abraham

Lakshmana M Anupindi

James A Rizzo

Parag Ranjan Maharana

Mark J Jander

Luke Everett McKay

Atul Mukker

Brandon L Hunt

Rajesh Prabhakaran

R Brian B Skinner

Chennakesava Arnoori

A redundant array of independent drives controller and board controlled cache off-loading during a power failure is described. Methods associated with the use of the redundant array of independent drives controller and board for controlled cache off-loading during a power failure are also described.

Control logic design to support USB cache offload

Systems and methods presented herein provide for resetting a controller in a Single Root Input/Output Virtualization (SR-IOV) architecture. The architecture includes a physical function that periodically issues a heartbeat command to a physical function of an SR-IOV controller, starts a first timer, determines a firmware failure of the controller upon expiration of the first timer, and issues a command to reset the firmware of the controller. The architecture also includes a plurality of a virtual function drivers coupled to a plurality of virtual functions of the controller. Each virtual function driver periodically issues a heartbeat command to its corresponding virtual function, starts a second timer having a duration that is less than a duration of the first timer, determines a firmware failure of the controller upon expiration of the second timer, and pauses input/output operations to its corresponding virtual function until the firmware of the controller is reset.

Virtual function timeout for single root input/output virtualization controllers

In one embodiment, a Peripheral Component Interconnect Express (PCIe) Input/Output (I/O) device operable to perform Single Root I/O Virtualization (SR-IOV) is provided. The device comprises hardware registers implementing a PCIe configuration space for the device, and firmware implementing one or more SR-IOV virtual functions that each provide a virtual machine access to a subset of PCIe configuration space hardware registers for the device. The device further includes a hardware recovery register directly accessible by each of the virtual machines, and a control unit. The control unit is operable to detect a firmware fault at the I/O device and to update the hardware recovery register with information describing the firmware fault.

Methods and structure for single root input/output virtualization enhancement in peripheral component interconnect express systems

Methods and structure for enabling re-training of a DDR memory controller in a storage device without loss of data in the DDR memory devices of the cache memory in response to detecting failure of the memory subsystem during operation of the storage device. In response to detecting a failure of the memory subsystem, the memory controller is reset without resetting the memory devices. The memory controller is then re-trained for operation with the memory device. During the re-training, self-refresh mode of the memory devices is disabled and manual refresh is performed by a processor of the storage device to thereby retain any user data in the memory device.

Methods and structure to assure data integrity in a storage device cache in the presence of intermittent failures of cache memory subsystem

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Lilburn, GA, United States of America

Moby J Abraham