Vlsi Technology, Inc.

Vsli Technology, Inc.

Aernos, Inc.

Moazzem M Hossain

Sunil V Ashtaputre

Mark R Hartoog

Siu-Tong Hui

Ying-Meng Li

Jacob Greidinger

Bala Thumma

Sundip R Doshi

Albert Chen

Herve Lambert

A sensor system in a package, comprising: a package, the package including: a sensor chip comprising sensor array comprising a plurality of sensing elements, wherein each of the plurality of sensing elements are functionalized with a deposited mixture consisting of hybrid nanostructures and a molecular formulation specifically targeting at least one of a plurality of gases, and wherein each of the plurality of sensing elements comprises a resistance and a capacitance, and wherein at least one resistance and capacitance are altered when the interacting with gaseous chemical compounds; and a mixed signal System on a Chip (SoC), comprising an analog signal conditioning and Analog-to-Digital conversion circuit configured to convert the analog signal into a digital signal, and a low-power processor circuit configured to processes the digital signal using a pattern recognition system implementing gas detection and measurement algorithms.

Systems and methods for an SoC based electronic system for detecting multiple low concentration gas levels

A method for laying out an integrated circuit design based upon a netlist provided by a behavioral synthesis tool includes the steps of: (A) placing cells specified by the netlist in a layout area in a placement step, the cells including pins that are interconnected by nets; (B) verifying timing constraints in a timing verification step of the placed cells in the layout area; and (C) if the timing verification step indicates that timing does not verify in that the timing constraints are not met: (a) modifying the netlist pursuant to an engineering change order (ECO); and (b) making an ECO placement of at least one cell into the layout area by (i) picking an unplaced cell from a set of unplaced cells to be a picked cell; (ii) determining a target window within said layout area for the placement of said picked cell; (iii) mapping said picked cell inside said target window; (iv) removing said picked cell from said set of unplaced cells; (v) optimizing the placement of said picked cell by analyzing said picked cell within said target window with respect to other cells, and modifying said placement of said picked cell if it improves timing; and (vi) repeating steps (i)-(v) until said set of unplaced cells is empty. A layout tool implements the method on a computer system to form a portion of an integrated circuit fabrication system.

Method and apparatus for improving engineering change order placement in

The present invention discloses a method and an apparatus for making digital integrated circuits by considering ramp delay and clock skew as constraints while minimizing the number of inserted buffers and overall wire length connecting components for large clock trees. The invention includes developing a set of circuit specifications including maximum clock skew, minimum driveability, and maximum ramp delay. These specifications are described in a hardware description language on a digital computer system, and a netlist is synthesized from this hardware description. A modified netlist is then formed by analyzing the netlist and inserting buffers into it to satisfy the circuit specifications of skew, driveability, and ramp delay. Thereafter, a digital integrated circuit is produced as specified by the modified netlist.

Method and apparatus for making integrated circuits by inserting buffers

A method for laying out an integrated circuit design based upon a netlist provided by a behavioral synthesis tool includes the steps of: (a) placing cells specified by the netlist in a layout area in a placement step, the cells including pins that are interconnected by nets; (b) verifying timing constraints in a timing verification step of the placed cells in the layout area; and (c) if the timing verification step indicates that timing does not verify in that the timing constraints are not met: (i) modifying the netlist pursuant to an engineering change order (ECO); and (ii) making an ECO placement of at least one cell into the layout area based upon the timing constraints while adjusting any affected nets as specified by the netlist. A layout tool implements the method on a computer system to form a portion of and integrated circuit fabrication system.

Method and apparatus for implementing engineering change orders in

The present invention discloses a method and an apparatus for making digital integrated circuits by considering ramp delay and clock skew as constraints while minimizing the number of inserted buffers and overall wire length connecting components for large clock trees. The invention includes developing a set of circuit specifications including maximum clock skew, minimum driveability, and maximum ramp delay. These specifications are described in a hardware description language on a digital computer system, and a netlist is synthesized from this hardware description. A modified netlist is then formed by analyzing the netlist and inserting buffers into it to satisfy the circuit specifications of skew, driveabilility, and ramp delay. Thereafter, a digital integrated circuit is produced as specified by the modified netlist.

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San Jose, CA, United States of America

Moazzem M Hossain