Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Matsushita Electronic Industrial Co., Ltd

Matsushita Electric Ind., Ltd.

Mizuki Segawa

Takashi Uehara

Toshiki Yabu

Takashi Nakabayashi

Atsushi Hori

Masatoshi Arai

Takaaki Ukeda

Takayuki Yamada

Yoshiaki Kato

Hiroaki Nakaoka

Hiroshi Shimomura

Kyoji Yamashita

Mitsuo Yasuhira

Hiroshi Masuda

Shuichi Kameyama

Michikazu Matsumoto

Akihira Shinohara

Ichiro Matsuo

Isao Miyanaga

Akira Matsuzawa

Masahiro Yasumi

Masaru Moriwaki

Minoru Fujii

Kiyoyuki Morita

Masahiro Fukui

Takehiro Hirai

Kunitoshi Aono

Akihiko Ohtani

Toshiro Akino

Nobuyuki Tamura

Kazuya Kikuchi

Ichirou Matsuo

Shunsuke Kugo

Takayuki Minemaru

Takayuki Matsuda

Takehisa Kishimoto

Tadashi Fukumoto

A plurality of metal wires are formed on an underlying interlayer insulating film. Areas among the metal wires are filled with a buried insulating film of a silicon oxide film with a small dielectric constant (i.e., a first dielectric film), and thus, a parasitic capacitance of the metal wires can be decreased. On the buried insulating film, a passivation film of a silicon nitride film with high moisture absorption resistance (i.e., a second dielectric film) is formed, and thus, a coverage defect can be avoided. A bonding pad is buried in an opening formed in a part of a surface protecting film including the buried insulating film and the passivation film, so as not to expose the buried insulating film within the opening. Thus, moisture absorption through the opening can be prevented. In this manner, the invention provides a semiconductor device which has a small parasitic capacitance in an area with a small pitch between the metal wires and is free from a coverage defect as well as the moisture absorption through the opening for the bonding pad, and a method of manufacturing the semiconductor device.

Semiconductor interconnect formed over an insulation and having moisture resistant material

A semiconductor device includes a transistor of a first conductivity type and a transistor of a second conductivity type. The transistor of the first conductivity type includes a first gate portion formed on a first region of a semiconductor substrate, a first sidewall formed on each side face of the first gate portion, a first protecting film formed between the first sidewall and the first gate portion, and an extension diffusion layer of the first conductivity type. The transistor of the second conductivity type includes a second gate portion formed on a second region of the semiconductor substrate, a second sidewall formed on each side face of the second gate portion, a second protecting film having an L-shaped cross-section and formed between the second sidewall and the second gate portion and between the second sidewall and the semiconductor substrate, and an extension diffusion layer of the second conductivity type.

Semiconductor device and method for fabricating the same

An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.

Semiconductor device and method of manufacturing the same

A conductive film for gate electrode including a polysilicon film is deposited on a semiconductor substrate, and patterned to form gate electrodes. An oxide film is formed on each side face of at least the polysilicon film, and by nitriding at least the surface portion of the oxide film, a nitride oxide film is formed on each side face of the gate electrodes. An interlayer insulating film is then deposited, and contact holes are formed through the interlayer insulating film. The existence of the nitride oxide film suppresses variation and reduction in size due to oxidation and etching of the gate side faces during resist removal and washing.

An inventive semiconductor device includes: a substrate; a plurality of first projections each including at least a gate electrode and formed on the substrate; and a plurality of second projections formed on the substrate. When a contour surface constituted by the uppermost face of the substrate and by side and upper faces of the first and second projections is measured for every partial area per unit area of the substrate, the maximum partial area of the contour surface is 1.6 or less times larger than the minimum partial area of the contour surface.

Semiconductor device utilizing dummy features to form uniform sidewall structures

A gate insulating film, a gate electrode, a gate-top protection film, LDD layers and nitride film sidewalls are formed on a semiconductor substrate. Source/drain regions are formed in the semiconductor substrate. After deposition of an interlayer insulating film on the resultant substrate, a hole is formed through the interlayer insulating film and the gate-top protection film to reach the gate electrode, and a gate contact is formed by filling the hole. The gate-top protection film has an opening exposing part of a portion of the area on the top surface of the gate electrode other than the region in contact with the gate contact. This facilitates external diffusion of hydrogen during annealing, or recovery from a fixed level and a damage layer during sintering.

Gate insulating film, gate electrode made up of lower and upper gate electrodes, and on-gate passivation film are formed in this order on an Si substrate. Then, a sidewall is formed as a stack of an oxynitride sidewall having an L-shaped cross section and a nitride sidewall, so as to surround the gate electrode and on-gate passivation film. Alternatively, only the lower edge of an L-oxide sidewall may be changed into an oxynitride region. Or an oxide or stacked sidewall and a nitride sidewall, covering the oxide or stacked sidewall, may be formed instead of the oxynitride sidewall. In any of these embodiments, the lower edge of the sidewall is not removed during a wet etching process.

Semiconductor device and method for facticating the same

An isolation is formed in a part of a P-well of a semiconductor substrate. A resistor film as a first conductor member is formed on the isolation. An insulating film covering the resistor film except for contact formation regions and an upper electrode film as a second conductor member are formed simultaneously with the formation of a gate electrode and a gate oxide film. Silicide films of a refractory metal are formed on the respective surfaces of the gate electrode, N-type high-concentration diffusion layers, the contact formation regions of the resistor film, and the upper electrode film. By utilizing a salicide process, a resistor and an inductor each occupying a small area can be formed without lowering the resistance of the resistor film. A capacitor, the resistor, and like component are selectively allowed to function.

An n-channel active region, a p-channel active region and an isolation insulating film are formed, and a silicon film is deposited via a gate insulating film. After introducing n-type impurities into the n-channel region and p-type impurities into the p-channel region, a silicon gate electrode is formed in such a manner that its width is enlarged only in the boundary portion between the n-channel region and the p-channel region. After forming a side wall insulating film, an n-channel diffusion layer and a p-channel diffusion layer, a metal silicide layer is formed in a self-aligned manner on the surfaces of the silicon gate electrode, the n-channel diffusion layer and the p-channel diffusion layer.

Semiconductor device with varying width electrode

After P ions are implanted into a polysilicon film in an nMOSFET region, a heat treatment is performed to diffuse phosphorus down to the lower part of the polysilicon film. The diffusion reduces the concentration of phosphorus in an upper end portion of the polysilicon film and inhibits the upper end edges of a gate electrode from being increased in size during patterning. Then, B ions are implanted into the polysilicon film in a pMOSFET region and the polysilicon film is etched into a gate configuration. Since a heat treatment for simultaneously diffusing phosphorus and boron in the polysilicon film is not performed, the entrance of boron from the gate electrode into a semiconductor substrate is inhibited, while the occurrence of side etching during the formation of an n-type polysilicon gate is suppressed.

Method of fabricating semiconductor device

Growing community of inventors

Osaka, Japan

Mizuki Segawa