Kabushiki Kaisha Toshiba

Mizuho Imai

Hiroshi Iwahashi

Masamichi Asano

Yuuichi Tatsumi

Hidenobu Minagawa

Hiroto Nakai

In a nonvolatile semiconductor memory device, a wiring layer is connected between a power source and a memory cell. Resistance of the wiring layer is larger than the on-resistance of a load transistor, so that the load transistor substantially determines the load characteristic. Therefore, the load characteristic curve is more gentle in inclination and more rectilinear in shape. This makes the data writing operation stable against a variance in the channel lengths of manufactured transistors forming the memory cells.

Nonvolatile semiconductor memory device

A semiconductor memory device includes word lines selectively driven by a signal from a row decoder, memory cells connected to word lines, first and second data lines, a bit line connected to receive data from the memory cell and to supply received data to the first data lines, dummy cells connected to word lines, first and second dummy data lines, a dummy bit lines connected to receive data from the dummy memory cell and to supply received data to the first dummy data line, a data sensing circuit for generating an output signal corresponding to a potential difference between the second data line and second dummy data line, a first MOS transistor connected between the first and second data lines, a first load circuit for charging the second data line, a second MOS transistor connected between the first and second dummy data lines, and a second load circuit for charging the second dummy data lines. The memory device further includes a first equalizer circuit connected between the second data line and dummy data line and equalizing potentials at both ends during a predetermined period of time after the semiconductor memory device is set in the active mode, and a second equalizer circuit connected between the data line and dummy data line and equalizing potential as at both ends during a predetermined period of time after the memory device is set in the active mode.

Semiconductor memory device having transfer gates which prevent high

Nonvolatile semiconductor memory device with stabilized data write

A semiconductor memory device in which data can be read out in response to an address signal comprises power source lines, a plurality of row and column conductive lines, a memory cell array including nonvolatile memory cells arranged in a matrix form of rows and columns and respectively connected to the plurality of row and column lines and the power source lines, a first selector circuit for generating a signal for selecting the row conductive lines in response to an address signal, a dummy row line, and a dummy memory cells each having a source, a drain and a control gate connected to the dummy row line. In the semiconductor memory device, one of paths between the source and the power source line and between the drain and the corresponding row line is closed and the other path is opened, and it further includes a second selector circuit for selectively generating a line selection signal for selecting one of the row conductive lines in response to an address signal and a dummy selection signal for selecting the dummy row line in response to the same address signal.

Semiconductor memory device having a test cell array

A semiconductor integrated circuit includes a CMOS circuit operated on a voltage of a first voltage level to set an output node thereof to a voltage of the first voltage level or a reference voltage; an output circuit for controlling supply of a voltage of a second voltage level which is higher than the first voltage level to a signal output node; and an isolation MOS transistor having a current path connected between the output node of the CMOS circuit and the signal output node and a gate connected to receive a control signal. The output node of the CMOS circuit is set to the reference voltage with the conduction resistance of the isolation MOS transistor kept high after the lapse of period in which the voltage of the second voltage level is kept supplied to the signal output node. After this, the conduction resistance of the isolation MOS transistor is reduced in response to the control signal.

High voltage booster circuit for use in EEPROMs

A semiconductor integrated circuit includes an output circuit and a control circuit for controlling the output circuit. The control circuit controls the output circuit so as to charge or discharge a preset node in the output circuit at a rate different from an ordinary charging or discharging rate for a preset period of time after a control signal has been changed in level.

Output circuit of semiconductor integrated circuit device

A semiconductor memory device has a redundancy circuit for compensating a defective bit when it occurs in the main memory cells. The redundancy circuit includes spare memory cells, a spare row decoder for selecting the spare memory cells, a first circuit section for inhibiting the use of the main row decoder when the spare row decoder is used, and a second circuit section for selecting the spare row decoder when an address specifying the main row line connected to the defective memory cell is denoted.

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Annaka, Japan

Mizuho Imai