Sanyo Electric Co., Ltd.

Miyuki Okamoto

Masato Fuma

Takao Inoue

Nagatoshi Sugihara

Yutaka Tamura

Fumiaki Nagao

Satoshi Kanai

An error correction circuit capable of detecting burst errors included in a data signal with reliability. The error correction circuit comprises a reading unit, a first estimation unit, a second estimation unit, and a correction unit. The reading unit reads the data signal. The first estimation unit estimates error locations based on BIS code included in the data signal, and stores the locations into an error location storing unit. The second estimation unit estimates error locations based on characteristics of bit strings adjoining the BIS code, and stores the locations into the error location storing unit. The correction unit identifies erasure locations based on the error locations stored in the error location storing unit, and performs erasure correction on the erasure locations identified. Since the error locations are estimated based on the BIS code and the characteristics of the bit strings adjoining the BIS code as well, it is possible to detect burst errors without fail.

Method of detecting error location, and error detection circuit, error correction circuit, and reproducing apparatus using the method

A method according to the present invention generates weight data for each audio band and assigns a number of bits to each band according to the weight data. The method then calculates a total of the numbers of bits of one block and compares the total with an upper limit and with a lower limit of a compression target value. Based on the comparison result, the method increases or decreases the value of the weight data to update it. The method reassigns a number of bits based on the updated weight data.

Method and apparatus for subband coding, allocating available frame bits based on changable subband weights

User data transmitted from the host side is first stored in write cache regions of an SDRAM on the basis of an error correction process. When executing an ECC&bull;EDC encode process of adding redundancy data such as an error correction code to the stored user data on the basis of the error correction processing, an encode region of SDRAM is used. The data subjected to the ECC&bull;EDC encode process is sequentially read out from encode region to be modulated and then written onto a disk.

Write cache circuit, recording apparatus with write cache circuit, and write cache method

A synchronous circuit which detects a detection synchronizing signal generated from a reproduction signal in a detecting window having a prescribed time width, and in a detecting window having a prescribed time width, and generates a frame synchronizing signal. The synchronous circuit includes a counter for counting how many times detection synchronizing signals are not consecutively detected, and a detecting window width determining unit for increasing the time width of the detecting window if, as a result of comparison between a value counted by the counter and a prescribed value set in advance, the counted value reaches the prescribed value.

Synchronous circuit and optical disk reproduction device capable of

An audio data dubbing system includes a reproduction side device and a recording side device. The reproduction side device reproduces intermittently from a reproduction side disc compressed audio data on the basis of a predetermined reproducing unit, which is first stored in a reproduction side memory and read out continuously therefrom to be provided as compressed audio data for recording. Recording side device first stores in a recording side memory compressed audio data for recording provided from the reproduction side device and reads out the same therefrom intermittently in a predetermined recording unit to be recorded on a recording side disc. The recording side device suspends the reproduction operation of compressed audio data from the reproduction side disc in the reproduction side device when the data amount in the recording side memory is increased to exceed a first reference value. The reproduction side device suspends the recording operation of the compressed audio data for recording to the recording side disc in the recording side device when the data amount in the reproduction side memory is decreased to become lower than a second reference value.

Audio data recording/reproduction device having digital high speed

A disc recorder containing a compressed data memory for storing compressed audio data to be recorded to a disc or reproduced from a disc. When a reduction pause state is set during reproduction operation, reading out of data from a compressed data memory is limited. Therefore, discontinuity of reproduced audio at the time of pause cancellation is prevented. When a recording pause state is set during recording operation, the compressed data memory is made empty. Therefore, discontinuity of the recording audio is also prevented at the time of pause cancellation.

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Hashima, Japan

Miyuki Okamoto