Fujitsu Corporation

Miyuki Ishida

Takashi Chiba

Naozumi Aoki

Isao Azuma

A communication command control system among a plurality of CPUs includes a control apparatus for transmitting an acknowledge signal to a request signal and thereafter for transmitting receiving command data and status data. The control apparatus comprises a local system priority determining circuit for determining a priority of signal processor commands from a plurality of CPUs and a local/remote system priority determining circuit for determining the priority between a local SIGP command controller and a remote SIGP controller. The data transfer period of the response request is detected when a response request is transmitted from another CPU of SIGP command control apparatus to the local and local/remote priority determining circuits, by counting the transfer period of command data after the response request is received and the acknowledge signal is transmitted and by counting the transfer period of the status data received from the other CPU. The system judges the destination of a CPU-ID representing the destination of said acknowledge signal, command data and status data.

Communication command control system between CPUs

An electronic circuit device able to diagnose a status-holding circuit by scanning, the device comprising a first plurality of integrated circuits each including a serial scan circuit for receiving serial data, generating an address value of a target status-holding circuit as parallel data from the received serial data, and selecting the target status-holding circuit having the generated address value, and a second plurality of integrated circuits each including a parallel scan circuit for receiving an address value of a target status-holding circuit as parallel data and selecting the target status-holding circuit having the received address value. Address information received as serial data being used for generating parallel address information, and address information received as parallel data being used for generating serial address information.

Electronic circuit device able to diagnose status-holding circuits by

A tag control circuit is provided in a memory access control apparatus of a digital computer system which also includes a central processor having a buffer storage. The tag control circuit includes a tag information store and update circuit and a necessity operation circuit for determining whether invalidation of the tag information and whether transmission of an invalidation information to the central processor are necessary. The tag control circuit also includes a first storage for storing a plurality of access requests of the invalidation operation determined by the necessity operation circuit, a second storage for storing a plurality of invalidation execute information determined by the necessity operation circuit, and a selection circuit receiving a new access request and an access request stored in the first storage and outputting one access request. The tag control circuit may further include a third circuit storage for storing only store access requests before supplying them to the necessity operation circuit, the third storage having an output connected to the request receiving and outputting circuit. The access selection circuit may output one request at a time the following priority order: a new read access request before an access request stored in the first storage and either before a store access request stored in the third storage.

Growing community of inventors

Kawasaki, Japan

Miyuki Ishida