Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Miwako Suzuki

Masatoshi Arai

Tsuyoshi Ohta

Norio Yasuhara

According to one embodiment, a semiconductor package includes a semiconductor chip, a sealing resin that has a flat plate shape and seals the semiconductor chip inside, a first electrode that includes a first mounting surface exposed on a first main face of the sealing resin, a second electrode that includes a second mounting surface exposed on the first main face, and a groove provided on the first main face. The first mounting surface includes a first end portion arranged in an inner region of the first main face and opposed to the second electrode. The groove includes a first connection portion connected to the first end portion, and a second connection portion connected to a lateral face of the sealing resin.

Semiconductor package

According to one embodiment, a semiconductor device includes a drift layer. The device includes a base layer. The device includes a source layer selectively provided on a surface of the base layer. The device includes a gate electrode provided via a gate insulating film in a trench penetrating the source layer and the base layer to reach the drift layer. The device includes a field plate electrode provided under the gate electrode in the trench. The device includes a drain electrode electrically connected to the drift layer. The device includes a source electrode. The field plate electrode is electrically connected to the source electrode. An impurity concentration of a first conductivity type contained in the base layer is lower than an impurity concentration of the first conductivity type contained in the drift layer. And the impurity concentration of the first conductivity type contained in the drift layer is not less than 1&#xd7;10(atoms/cm).

Semiconductor transistor device and method for manufacturing same

According to one embodiment, the semiconductor device includes a first semiconductor layer. The semiconductor device includes a plurality of base regions, the base regions are provided on a surface of the first semiconductor layer. The semiconductor device includes a source region selectively provided on each of surfaces of the base regions. The semiconductor device includes a gate electrode provided via a gate insulating film in each of a pair of trenches, each of the trenches penetrate the base regions from a surface of the source region to the first semiconductor layer. The semiconductor device includes a field plate electrode provided via a field plate insulating film in each of the pair of trenches under the gate electrode. A thickness of a part of the field plate insulating film is greater than a thickness of the gate insulating film.

Semiconductor device and method for manufacturing same

According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type and a first electrode. The second regions are provided separately on a first major surface side of the first layer. The third region is provided on the first major surface side of the first layer so as to surround the second regions. The first electrode is provided on the first layer and the second regions. The first layer has a first portion and a second portion. The second portion has a lower resistivity than the first portion. The second portion is provided between the second regions and between the first portion and the first major surface and is provided outside the third region and between the first portion and the first major surface.

Semiconductor device

A semiconductor layer has a second impurity concentration. First trenches are formed in the semiconductor layer to extend downward from an upper surface of the semiconductor layer. Each of insulation layers is formed along each of the inner walls of the first trenches. Each of conductive layers is formed to bury each of the first trenches via each of the insulation layers, and extends downward from the upper surface of the semiconductor layer to a first position. A first semiconductor diffusion layer reaches a second position from the upper surface of the semiconductor layer, is positioned between the first trenches, and has a third impurity concentration lower than the second impurity concentration. A length from the upper surface of the semiconductor layer to the second position is equal to or less than half a length from the upper surface of the semiconductor layer to the first position.

Growing community of inventors

Kanagawa-ken, Japan

Miwako Suzuki