Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Mitsuyuki Kunieda

Hiroaki Suzuki

Kenji Matsuo

Itsuo Sasaki

Tadahiro Fujii

A semiconductor IC includes a first logic circuit, having a first threshold voltage, for outputting a logic signal corresponding to a level of an input signal which is externally supplied thereto, and an internal circuit for receiving a logic signal from the first logic circuit and executing a predetermined operation. The semiconductor IC further includes a second logic circuit, formed between the first logic circuit and the internal circuit, and having a second threshold voltage higher than the first threshold voltage, one input terminal thereof being connected to an output terminal of the first logic circuit, and the other input terminal receiving a control signal. The control signal is generated while power source noise caused by an operation of the internal circuit is being generated. While the control signal is being generated, a signal of a predetermined logic level is supplied from the second logic circuit to the internal circuit, regardless of an output signal level from the first logic circuit.

Semiconductor IC including circuit for preventing erroneous operation

A MOS logic circuit comprises two P channel MOSFETs connected in parallel between a positive power source V.sub.DD and a logic signal output terminal and two series circuits connected in parallel between a ground voltage source V.sub.SS and the terminal, each series circuit being comprised of serially connected two N channel MOSFETs. The gate electrodes of the MOSFETs located in the corresponding positions in the respective series circuits are connected to first and second logic signal input terminals, respectively. Similarly, the gate electrodes of the other MOSFETs located in the corresponding positions in the respective series circuits are connected to the second and first logic signal input terminals, respectively.

Growing community of inventors

Kawasaki, Japan

Mitsuyuki Kunieda