Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Matsushita Electric Industrial Co., Ltd.

Mitsuyoshi Mori

Yutaka Hirose

Toru Okino

Yusuke Sakata

Takumi Yamaguchi

Ryohei Miyagawa

Yoshihisa Kato

Kazuo Fujiwara

Takahiko Murata

Hiroshi Masuda

Yusuke Otake

Yoshihiro Sato

Motonori Ishii

Yoshiyuki Ohmori

Hitoshi Kuriyama

Shigetaka Kasuga

Mikiya Uchida

Akito Inoue

Yasuhiro Shimada

Daisuke Ueda

Hirohisa Ohtsuki

Hideyuki Arai

Manabu Usuda

Yuki Sugiura

Kentaro Nakanishi

Takuma Katayama

Tatsuya Kabe

Hisashi Aikawa

Tsuyoshi Tanaka

Shinji Yoshida

Takayoshi Yamada

Keisuke Tanaka

Toshinobu Matsuno

Shigeru Saitou

Hiroyuki Doi

Masafumi Tsutsui

Shinzou Kouyama

Kenji Taniguchi

Masayuki Furuhashi

A solid state image sensor includes at least a plurality of pixel cells and a vertical scanning circuit. Each of the pixel cells includes an avalanche photodiode, a floating diffusion portion, a transfer transistor, a reset transistor, an amplifier transistor, a selection transistor, a count transistor, and a capacitor. The amplifier transistor outputs a voltage signal responsive to the amount of charge stored in the floating diffusion portion. The capacitor has terminals one of which is connected to the count transistor. The vertical scanning circuit is configured to be able to supply different levels of voltages to the other terminals of the capacitors.

Solid-state imaging sensor

A light detector is configured such that a light receiving portion having APDs and a peripheral portion are provided on a first principal surface of a p-type semiconductor substrate, and further includes a back electrode provided on a second principal surface of the semiconductor substrate and a p-type first separation portion provided between the light receiving portion and the peripheral portion. The APD has, on a first principal surface side, an n-type region and a p-epitaxial layer contacting the n-type region in a Z-direction. The peripheral portion has an n-type MISFET provided at a p-well and an n-well provided to surround entire side and bottom portions of the p-well.

Light detector

A light detector is configured such that a light receiving portion having APDs and a peripheral circuit portion are provided on a first principal surface of a p-type semiconductor substrate, and further includes a back electrode provided on a second principal surface of the semiconductor substrate and a p-type first separation portion provided between the light receiving portion and the peripheral circuit portion. The APD has, on a first principal surface side, an n-type region and a p-epitaxial layer contacting the n-type region in a Z-direction. The peripheral circuit portion has an n-type MISFET provided at a p-well and an n-well provided to surround side and bottom portions of the p-well.

A photodetector includes: at least one avalanche photodiode including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type; a first transistor connected to the first semiconductor layer and including a channel of the second conductivity type that has polarity opposite to polarity of the first conductivity type; and a second transistor connected to the first semiconductor layer and including a channel of the first conductivity type.

Photodetector, photodetector array, and drive method comprising a second transistor including a channel of first conductivity type and a first transistor including a channel of second conductivity type that has polarity opposite to polarity of the first conductivity type

A photodiode that multiplies a charge generated by photoelectric conversion in an avalanche region includes: a p&#x2212; type semiconductor layer having interfaces; an n+ type semiconductor region located inside the p&#x2212; type semiconductor layer and in contact with the interface; an n+ type semiconductor region located inside the p&#x2212; type semiconductor layer and connected to the n+ type semiconductor region; and a p type semiconductor region located between the n+ type semiconductor region and the interface, wherein the n+ type semiconductor region, the n+ type semiconductor region, and the p type semiconductor region each have a higher impurity concentration than the p&#x2212; type semiconductor layer, the avalanche region is a region between the n+ type semiconductor region and the p type semiconductor region inside the p&#x2212; type semiconductor layer, and the n+ type semiconductor region has a smaller area than the n+ type semiconductor region in planar view.

Photodiode, photodiode array, and solid-state imaging device

An imaging device includes: a photoelectric converter which converts light into signal charges; a charge accumulation region which is electrically connected to the photoelectric converter, and accumulates the signal charges; a transistor having a gate electrode which is electrically connected to the charge accumulation region; and a contact plug which electrically connects the photoelectric converter to the charge accumulation region, is in direct contact with the charge accumulation region, and comprises a semiconductor material.

Solid-state imaging device

A solid-state imaging device includes: a first electrode formed above a semiconductor substrate; a photoelectric conversion film formed on the first electrode and for converting light into signal charges; a second electrode formed on the photoelectric conversion film; a charge accumulation region electrically connected to the first electrode and for accumulating the signal charges converted from the light by the photoelectric conversion film; a reset gate electrode for resetting the charge accumulation region; an amplification transistor for amplifying the signal charges accumulated in the charge accumulation region; and a contact plug in direct contact with the charge accumulation region, comprising a semiconductor material, and for electrically connecting to each other the first electrode and the charge accumulation region.

A solid-state imaging device includes a substrate of P type and a wiring layer. The substrate includes: a first semiconductor region disposed on a first principle surface and extending in a direction from the first principal surface toward the second principal surface; a second semiconductor region disposed between the second principal surface and the first semiconductor region and connected to the first semiconductor region; a P type semiconductor region disposed between the second principal surface and the second semiconductor regions of two pixels; and a pixel isolation region disposed inside the substrate, between the first semiconductor regions of the two pixels. The second semiconductor region and the P type semiconductor region form an avalanche multiplication region.

A solid-state imaging device according to the present disclosure includes pixels arranged two-dimensionally, each of the pixels including: a metal electrode; a photoelectric conversion layer that is on the metal electrode and converts light into an electrical signal; a transparent electrode on the photoelectric conversion layer; an electric charge accumulation region that is electrically connected to the metal electrode and accumulates electric charges from the photoelectric conversion layer; an amplifier transistor that applies a signal voltage according to an amount of the electric charges in the electric charge accumulation region; and a reset transistor that resets electrical potential of the electric charge accumulation region, in which the reset transistor includes a gate oxide film thicker than a gate oxide film of the amplifier transistor.

A solid-state imaging device according to the present disclosure includes: a charge storage region that stores a signal charge obtained through photoelectric conversion in a photoelectric conversion film; an amplification transistor that amplifies the signal charge stored in the charge storage region in a corresponding pixel; a contact plug that is electrically connected to the charge storage region and contains a semiconductor material; and a line that is disposed above the contact plug and contains a semiconductor material. The contact plug and the charge storage region are electrically connected, and the contact plug and a gate electrode of the amplification transistor are electrically connected via the line.

A solid-state imaging device includes: pixels arrayed two-dimensionally; pixel common circuits arrayed in a matrix, each shared by adjacent pixels of a certain number among the pixels; column common circuits, each provided for one of columns of the pixel common circuits, and shared by pixel common circuits belonging to a same column; column signal lines each provided for one of the columns of the pixel common circuits; and reset signal lines each provided for one of the columns of the pixel common circuits, in which an electric signal from each of the pixels is detected by a corresponding one of the pixel common circuits and read by a corresponding one of the column common circuits, and the electric signal detected by the corresponding one of the pixel common circuits is reset by a feedback path including one column signal line, one column common circuit, and one reset signal lines.

Solid-state imaging device having reduced &#x3ba;TC noises and method of driving the same

Growing community of inventors

Kyoto, Japan

Mitsuyoshi Mori