Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Mitsuya Kinoshita

Kazutami Arimoto

Fukashi Morishita

Tetsushi Tanizaki

Hiroshi Miyamoto

Atsushi Hachisuka

Takahiro Tsuruda

Takeshi Fujino

Mako Kobayashi

Teruhiko Amano

Shigeru Mori

Yoshikazu Morooka

Makoto Suwa

Shigeru Kikuda

Hideaki Arima

Kazuhiro Tsukamoto

Tatsuo Okamoto

Yoshinori Tanaka

Kiyohiro Furutani

Katsumi Dosaka

Shinya Watanabe

Toshiaki Ogawa

Moriaki Akazawa

Tatsuo Kasaoka

Takeshi Hamamoto

Tadaaki Yamauchi

Hideyuki Noda

Masaaki Mihara

Tadato Yamagata

Masaru Haraguchi

Michihiro Yamada

Toshifumi Kobayashi

Mitsue Takahashi

A test signal applied to an embedded memory is changed in synchronization with a test clock signal, set to an invalidated state by an asynchronous control signal asynchronous to the test clock signal and then is applied to a memory. The memory takes in a received signal in synchronization with a memory clock signal. An invalid data generating circuit modifies the test signal in accordance with the asynchronous control signal and generates a test signal and to apply the test signal to the memory. A period of an invalid state of the modified test signal can be adjusted and therefore, by monitoring a changing timing of the asynchronous control signal PTX with an external tester, setup and hold times of a signal for the memory can be measured. Setup and hold times and an access time for an embedded memory can be correctly measured.

Test circuit capable of testing embedded memory with reliability

An XOR gate receives an input from a pair of read data lines to output a self-precharge signal when there is an increased potential difference between the paired read data lines. Thus, immediately after the increased potential difference between the paired read data lines occurs upon issuance of a read command, a precharge operation is autonomically performed. Therefore, no external precharge command is necessary when the read command is issued and thus a higher-speed operation is easily achieved.

Semiconductor memory device having self-precharge function

Internal read out data bits are divided into a plurality of data groups, and data bits in corresponding positions in different data groups are paired off. A determination gate is provided to each pair of data bits, and determining operation is performed in each pair to compress the result of determination to finally generate a 1-bit flag indicating a match/mismatch in logic level among the internal read out data. Consequently, a multi-bit test circuit that has a reduced layout area and can perform high-speed multi-bit determination is provided.

Multi-bit test circuit

In a semiconductor memory device having a shared sense amplifier configuration, a control circuit outputting a bit line isolation signal latches a block selection signal in accordance with a change in a trigger signal. With this configuration, when the same block is selected, no change is caused in the bit line isolation signal. Consequently, charge/discharge current is reduced, and power consumption is reduced. Since a specific bit in a refresh counter is not used, unlike the conventional technique, the design changes little even in the case of changing the configuration of an array.

Semiconductor memory device with reduced power consumption

A semiconductor memory device includes an isolation unit isolating a bit line in a first region including a memory cell formed of a thick film transistor and a second region including a sense amplifier formed of a thin film transistor. Voltage supply lines are provided corresponding to respective regions. In a test mode, the isolation unit isolates the two regions. A voltage for testing is supplied from the voltage supply line. Thus, a voltage for testing corresponding to a thick film transistor and a thin film transistor can be supplied to allow efficient execution of a burn-in test.

Semiconductor memory device with circuit executing burn-in testing

A contact hole having an opening diameter smaller than the minimum dimension that can be formed by photolithographic technique is formed. Using an interlayer insulating film formed on a semiconductor substrate as an etching mask, etching is carried out halfway to form an opening . The etching mask is removed, and a TEOS film is formed on the interlayer oxide film . The whole surface is then etched anisotropically to form a contact hole

Semiconductor device and a method of manufacturing thereof

A voltage down converter includes a first voltage down converting circuit and a second voltage down converting circuit. The first voltage down converting circuit supplies an internal power supply voltage VCCS to an internal circuit only during a period T when the internal power supply voltage VCCS falls below a predetermined voltage according to a signal DCE. In the first voltage down converting circuit, P channel MOS transistors are selectively activated according to the levels of the plurality of voltages, and a voltage down converting partial circuit supplies a current of an amount corresponding to the level of the external power supply voltage VCC to a power supply node. As a result, even during the period T, the internal power supply voltage can be maintained at a level of the reference voltage.

Voltage down converter allowing supply of stable internal power supply voltage

A power supply circuit and an oscillation circuit or the like of noise generation sources are concentrated, and the periphery thereof is surrounded by a guard ring. Guard ring is provided to have bonding pads at least partially thereon. Guard ring is effectively provided utilizing the region below bonding pads, so that effective noise reduction is achieved while preventing increase in chip area.

Semiconductor memory device capable of performing stable operation for noise while preventing increase in chip area

A control circuit portion which controls the operations of memory cells is concentrated in a central portion and heat radiation plates are placed thereon via adhesive. A semiconductor integrated circuit having a function of the MPU or the like is placed above the control circuit portion via a bump electrode. The control circuit portion and a memory block are formed on separate chips respectively.

Semiconductor memory device

A master control circuit provides access to a corresponding memory block via four local control circuits. The memory blocks are arranged so as to surround the master control circuit and the local control circuits. The amount of delay of a control signal to each memory block is set substantially equal to suppress skew in the control signal. A DRAM of high speed can be realized.

High speed operable semiconductor memory device with memory blocks arranged about the center

A contact hole having an opening diameter smaller than the minimum dimension that can be formed by photolithographic technique is formed. Using an interlayer insulating film 8 formed on a semiconductor substrate as an etching mask, etching is carried out halfway to form an opening 8a. The etching mask is removed, and a TEOS film 10 is formed on the interlayer oxide film 8. The whole surface is then etched anisotropically to form a contact hole 11.

A voltage generation circuit includes a voltage comparing circuit to compare a reference voltage signal Vi and an internal power supply voltage Vcc and a current supply transistor to supply current based on the output voltage of the voltage comparing circuit and maintain Vcc. The voltage generation circuit also includes a reference voltage signal generation circuit which responds to a control signal ACT activated for a prescribed time period prior to the operation timing of a load and sets Vi=Vref when control signal ACT is inactive and Vi=Vref+.DELTA.V when control signal ACT is active.

Voltage generation circuit capable of supplying stable power supply

High speed operable semiconductor memory device with memory blocks

A rectangular semiconductor substrate region is divided into regions arranged in a plurality of rows and columns, and memory array blocks are provided to surround a central region. The plurality of memory array blocks are divided into a plurality of banks. Peripheral regions on both sides of the rectangular semiconductor substrate region are used as regions for providing sense amplifier power supply circuits, and circuits for generating a voltage to be transmitted onto word lines are provided at the four corner regions of the central region. Thus, a large storage capacity semiconductor memory device operating stably at a high speed and with reduced power consumption can be implemented.

Multi-bank clock synchronous type semiconductor memory device having

Regular memory cell arrays are arranged in divided regions in three rows and three columns except for the region located at the second row and the second column. The region located at the intersection of the second row and the second column is provided with a redundant memory cell array. The replacement operation of the regular memory cell arrays with the redundant memory cell array is provided for each memory cell block.

Growing community of inventors

Hyogo, Japan

Mitsuya Kinoshita