Hitachi, Ltd.

Mitsutoshi Uchida

Shigeyuki Nishitani

Naruhiko Kasai

Toshio Tanaka

Hiroyuki Mano

Tetsuya Suzuki

Hiroko Sato

Shinji Wakisaka

Tatsuzo Hamada

Kazuko Hasegawa

Hitoshi Kawaguchi

Yasuo Kurosu

Shigeo Tsujioka

Kazumi Kubota

Kensuke Ooyu

A liquid crystal display system which can accept input display data having a resolution which is larger (e.g. 1120&times;780 dots) or smaller (e.g. 640&times;480 dots) than a resolution of a liquid crystal panel (e.g. 1024&times;768 dots), and convert the input display data to reduced or enlarged display data for display on the liquid crystal panel. The system generates, for example, one new vertical or horizontal line based on two contiguous vertical or horizontal lines in the input display data. If the resolution of the input display data is larger than the resolution of the liquid crystal panel, the system replaces the two contiguous lines with the one new line. If the resolution of the input display data is smaller than the resolution of the liquid crystal panel, the system inserts the one new line between the two contiguous lines.

Liquid crystal display system capable of reducing and enlarging resolution of input display data

A liquid crystal display system which can accept display data having a resolution different from that of a screen for the liquid crystal display and display the display data. For example, a CPU outputs display data of 1120&times;780 dots and a liquid crystal panel has a 1024&times;768-dot resolution which is smaller than the display data resolution. The display screen of the liquid crystal panel comprises a linear arrangement of pixels. A data conversion section generates display data for a new horizontal or vertical line based on display data for two horizontal or vertical lines contiguous to each other and repeats replacement of display data of the two lines with the display data of the one line for reducing the number of horizontal lines of one screen and the number of dots of one line so as to match the resolution of the display data output by the CPU with the liquid crystal display. In contrast, if the resolution of the display data is smaller than the screen resolution of the liquid crystal panel, the data conversion section inserts the display data of the new one horizontal or vertical line between the two contiguous lines for enlarging the resolution of the display data.

A liquid crystal display system which can accept display data having a resolution different from that of a screen for the liquid crystal display and display the display data. For example, a CPU outputs display data of 1120.times.780 dots and a liquid crystal panel has a 1024.times.768-dot resolution which is smaller than the display data resolution. The display screen of the liquid crystal panel comprises a linear arrangement of pixels. A data conversion section generates display data for a new horizontal or vertical line based on display data for two horizontal or vertical lines contiguous to each other and repeats replacement of display data of the two lines with the display data of the one line for reducing the number of horizontal lines of one screen and the number of dots of one line so as to match the resolution of the display data output by the CPU with the liquid crystal display. In contrast, if the resolution of the display data is smaller than the screen resolution of the liquid crystal panel, the data conversion section inserts the display data of the new one horizontal or vertical line between the two contiguous lines for enlarging the resolution of the display data.

Liquid crystal display system capable of reducing and enlarging

A data transfer control apparatus for a co-processor system. The co-processor system includes a memory; a memory bus connected to the memory; a main processor connected to the memory bus and having a control circuit for controlling data read/write relative to the memory, the main processor performing data transfer from/to the memory bus via a first data input/output terminal; and a co-processor connected to the memory bus via a second data input/output terminal. The control apparatus includes a high impedance setting circuit for selectively setting the first data input/output terminal at a high impedance state to electrically isolate the first data input/output terminal from the memory bus; and a control signal generator for selectively outputting a control signal to the high impedance setting circuit to cause the high impedance setting circuit to set the first data input/output terminal at the high impedance state. When the co-processor is to perform data read/write relative to the memory, the control signal generator generates the control signal to cause the high impedance setting circuit to set the first data input/output terminal at the high impedance state, and while the first data input/output terminal is set at the high impedance state, the main processor performs read/write control of the memory bus, and the co-processor performs data transfer from/to the memory bus via the second data input/output terminal.

Data transfer control method and apparatus for co-processor system

Growing community of inventors

Hadano, Japan

Mitsutoshi Uchida