Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Toshiba Memory Corporation

Mitsutoshi Nakamura

Kyoichi Suguro

Koji Shirai

Kazumi Nishinohara

Kazuya Nishihori

Keita Masuda

Ichiro Taguchi

Ryo Fukuda

Masaki Kondo

Yukihiro Ushiku

Yohji Watanabe

Shinya Naito

Masami Nagaoka

Hirotaka Amakawa

A semiconductor device includes an insulating layer, a semiconductor layer on the insulating layer, and a control electrode on the semiconductor layer. The semiconductor layer includes first and second semiconductor parts and a separation trench between the first and second semiconductor parts. The first and second semiconductor parts extending along the insulating film. The first semiconductor part includes first and second regions of a first conductivity type, and a fifth region of a second conductivity type between the first and second regions. The second semiconductor part includes third and fourth regions of the second conductivity type, and a sixth region of the second conductivity type between the third and fourth regions. The control electrode extends over the fifth and sixth regions. The semiconductor layer further including a seventh region of the second conductivity type at a bottom of the separation trench and electrically connecting the fifth and sixth regions.

Semiconductor device having semiconductor region at bottom of separation trench and connecting two semiconductor regions over which control electrode extends

A high frequency transistor includes a first semiconductor layer, a first insulating film and a control electrode. The first semiconductor layer on the first insulating film extends in a first direction along an upper surface of the first insulating film. The first semiconductor layer has a first layer thickness in a second direction perpendicular to the upper surface, and a first width in a third direction orthogonal to the first direction. The first width is greater than the first layer thickness. The control electrode covers upper and side surfaces of the first semiconductor layer. The first semiconductor layer includes a first region of a first conductivity type, second and third regions of a second conductivity type. The first to third regions are arranged in the first direction. The first region is provided between the second and third region. The control electrode covers the first region.

High frequency transistor

According to an embodiment, a process simulator has a layout processing unit to extract vertex coordinates of a first graphic of a layout of a semiconductor device described in a layout file used for a simulation, an initial mesh generation unit to generate a first initial mesh passing through the vertex coordinates in a plane direction of the layout, and a simulator unit to execute a process simulation of the semiconductor device based on simulation data in which a process flow of the semiconductor device is described, the layout, and the first initial mesh.

Process simulator, layout editor, and simulation system

A semiconductor memory device includes a semiconductor substrate, a stacked body provided on the semiconductor substrate, a semiconductor pillar and an electrode member provided inside the stacked body, a charge storage film, and a control circuit. The stacked body includes insulating films and electrode films stacked alternately. The semiconductor pillar and the electrode member extend in a stacking direction and lower ends thereof are connected to the semiconductor substrate. The charge storage film is provided between the semiconductor pillar and one of the electrode films. The control circuit sets an upper end of the semiconductor pillar to a floating state, applies a first potential to the semiconductor substrate, applies a second potential to the electrode member, and applies a third potential to the one of the electrode films. The second potential is lower than the first potential. The third potential is lower than the second potential.

Semiconductor memory device and method for driving the same

A semiconductor integrated circuit device according to an embodiment of the present invention includes: a semiconductor substrate; an internal circuit formed on the semiconductor substrate, a first potential and a second potential being supplied to the internal circuit, thereby applying an operating voltage to the internal circuit; a fuse disposed above a semiconductor region of a first conductivity type, and electrically connected to the internal circuit, the semiconductor region being supplied with the second potential and being formed in the semiconductor substrate; and a protective element formed in the semiconductor region of the first conductivity type and protecting the internal circuit in response to positive and negative abnormal voltages generated in a wiring through which the fuse and the internal circuit are connected to each other.

Semiconductor integrated circuit device

A method for optimizing a structure of an industrial product includes selecting control factors from among manufacturing parameters affecting a target characteristic, which is scheduled to be manufactured by a sequence of manufacturing processes; setting levels to the respective control factors; selecting a reference characteristic having a trade-off relation with the target characteristic from among characteristics of the structure; setting a reference value to the reference characteristic; selecting a prior adjustment factor affecting the reference characteristic; creating conditions for experiments assigning combinations of the levels to the respective control factors; determining an adjustment value of the prior adjustment factor so that each of characteristic values of the reference characteristic obtained by the experiments conforms substantially to the reference value; and determining experimental characteristic values of the target characteristic using the adjustment value.

Method for optimizing an industrial product, system for optimizing an industrial product and method for manufacturing an industrial product

A process of manufacturing a semiconductor device utilizing a thermo-chemical reaction is started based on preset initial settings, a state function of an atmosphere associated with the thermo-chemical reaction is measured, a state of the atmosphere and a change thereof are analyzed based on measurement data obtained by the measurement, and then, analysis data obtained by the analysis is fed back to a manufacturing process.

Method and apparatus for manufacturing semiconductor device, method and apparatus for controlling the same, and method and apparatus for simulating manufacturing process of semiconductor device

A semiconductor device includes a silicon substrate having a film thickness smaller than a maximum range of a particle generated by a nuclear reaction between a fast neutron and a silicon atom, and a semiconductor element formed on a surface of the silicon substrate.

Semiconductor device

A simulation method and a simulation apparatus suppress a parabolic increase in depth angle calculation time to a linear increase at most with respect to an increase in the number of depth angle calculation points on a surface string that represents a processing surface to be simulated. The simulation method and apparatus are applicable to a deposition process that deposits metal such as aluminum on a semiconductor substrate in a vacuum with the use of physical adsorption. The simulation method and apparatus are effective, in particular, to quickly calculate depth angles on a two-dimensional shape to a processing surface to which the deposition process is applied. The depth angles are angles in which particles fly toward the processing surface during the deposition process. The simulation method and apparatus trace a surface string representing the processing surface from the origin to the terminal thereof and find depth angles at all points on the surface string. If a supplement of adjacent segments on the surface string is negative, a depth angle at a node of the adjacent segments is calculated at once according to the supplement and a maximum or minimum angle already found at the preceding point. If a depth angle at a given point is not calculable based on the preceding point, a point that determines the depth angle is found in a segment list according to a bisection method.

Method and apparatus for string model simulation of a physical semiconductor process including use of specific depth angles and segment list with removal of redundant segments

A simulation method and a simulator determine a profile of particles, by determining whether or not each reaction formula, which describes a reaction of particles to generate reactants in semiconductor solids or gases, is in equilibrium, determining unknown variables excluding variables related to the reactants of each equilibrium reaction, forming continuity equations containing a plurality of time differential terms as functions of the unknown variables, linearizing and discretizing the time differential terms into the coefficient matrix and constant vector of simultaneous linear equations, and solving the simultaneous linear equations.

Growing community of inventors

Kanagawa, Japan

Mitsutoshi Nakamura