Fujitsu Corporation

Kyushu Fujitsu Electronics Limited

Fujitsu Semiconductor Limited

Other

Fujitsu Microelectronics Limited

Mitsutaka Sato

Tetsuya Fujisawa

Junichi Kasai

Yoshitaka Aiba

Toshio Hamano

Hirohisa Matsuki

Katsuhiro Hayashida

Yoshiyuki Yoneda

Masaaki Seki

Kazuto Tsuji

Ryuji Nomoto

Masanori Yoshimoto

Akira Takashima

Yoshihiro Kubota

Seiichi Orimo

Yoshitsugu Katoh

Hiroshi Inoue

Michio Sono

Masamitsu Ikumo

Hiroshi Yoshimura

Masaki Waki

Tadashi Uno

Kazuhiko Mitobe

Kaname Ozawa

Shigeyuki Maruyama

Masataka Mizukoshi

Eiji Watanabe

Toshimi Kawahara

Masaharu Minamizawa

Akira Okada

Yutaka Makino

Tetsuya Hiraoka

Mitsunada Osawa

Osamu Igawa

Mitsuo Abe

Shinichirou Taniguchi

Masahiko Ishiguri

Noriaki Shiba

Kouichi Takeshita

Kosuke Otokita

Tadahiro Okamato

Kazuhiko Kobayashi

Yasuhiro Suzuki

Atsushi Hatakeyama

Yasunori Fujimoto

Eiji Yoshida

Hideharu Sakoda

Fumio Baba

Kazuyuki Imamura

Masayoshi Hirata

Koju Aoki

Norio Taniguchi

Yuji Akashi

Hiroyuki Sakima

Michio Hayakawa

Hayato Okuda

Masahiko Harayama

Toyoshige Kawashima

Kousuke Otokita

A semiconductor device of the invention includes a substrate in which a power-supply electrode and a ground electrode are provided. A first semiconductor chip is disposed over the substrate and has a first conductor layer formed on a surface facing a second semiconductor chip. A second conductor layer is disposed over the first semiconductor chip and has a second conductor layer formed on a surface facing the first semiconductor chip. And an adhesive layer is disposed between the first conductor layer and the second conductor layer and bonds together the first semiconductor chip and the second semiconductor chip. In the semiconductor device, the adhesive layer and the first and second conductor layers function as a capacitor.

Adhesive layer forming a capacitor dielectric between semiconductor chips

A semiconductor device includes a first semiconductor chip () having a first terminal () on one surface, a second semiconductor chip () which is larger than the first semiconductor chip () and on which the first semiconductor chip () is stacked and which has a second terminal () on one surface, an insulating layer () formed on a second semiconductor chip () to cover the first semiconductor chip (), a plurality of holes () formed in the insulating layer () on at least a peripheral area of the first semiconductor chip (), a via () formed like a film on inner peripheral surfaces and bottom surfaces of the holes () and connected electrically to the second terminal () of the second semiconductor chip (), a wiring pattern () formed on an upper surface of the insulating layer (), and an external terminal () formed on the wiring pattern ().

Semiconductor device having a plurality of semiconductor chips and method for manufacturing the same

A semiconductor device with a structure having superior heat sink characteristics. A first heat sink member is located over a wiring board by using an adhesive material. A semiconductor element is stuck over the first heat sink member by using an adhesive material. The semiconductor element and electrodes located over the wiring board are connected by wires. A second heat sink member which covers the semiconductor element and the wires is joined to the first heat sink member by using a conductive adhesive material. The inside and outside of the second heat sink member are sealed by resin except a flat top thereof. By doing so, the semiconductor device is fabricated. Heat which is generated in the semiconductor element and which is transmitted to the first heat sink member is released from an edge portion of the first heat sink member. In addition, the heat which is generated in the semiconductor element and which is transmitted to the first heat sink member is transmitted to the conductive adhesive material and the second heat sink member and is released from the flat top of the second heat sink member.

Semiconductor device and method for fabricating the same

A method of design of a circuit board enabling high density conductor lines to be drawn efficiently. A rats nest is formed by connecting pads to which terminals of an electronic device are connected and external connection terminals by lines. A region with the highest density of lines of the rats nest is then selected and design rules relating to routes and dimensions of conductor lines are set in the region with the highest density of lines of the rats nest. Conductor lines are then laid at the region with the highest density of lines of the rats nest, and whether or not the conductor lines can be laid at the region with the highest density of lines of the rats nest is confirmed. Setting of the design rules and laying of conductor lines are if the conductor lines cannot be laid, and the conductor lines of the remaining regions are laid by the set design rules if the conductor lines can be laid.

Method of designing circuit board

The present invention realizes a miniaturized electronic device that is still capable of maintaining its high reliability even when miniaturized. To this end, the electronic device has an electronic circuit, comprising: a substrate with a circuit formation surface on which one part of the electronic circuit is formed; a polyimide layer that is formed on the circuit formation surface; and a spiral inductor constituting another part of the electronic circuit, which is formed into a pattern on the polyimide layer.

Electronic device

A semiconductor device including a semiconductor element having an electrode pad, a mounting terminal for mounting a substrate, an adhesive layer provided on the semiconductor element, and a wiring electrically connecting the electrode pad to the mounting terminal. The wiring includes a metal foil and a metal film layer. The entire metal foil is in contact with the adhesive layer, and the metal film layer is in contact with the electrode pad.

Semiconductor device manufacturing method having a step of applying a copper foil on a substrate as a part of a wiring connecting an electrode pad to a mounting terminal

There are provided a sealing insulating film that is formed on a substrate and melted at a first heating temperature to have a flowability, and external terminals that are formed on the substrate, and connected to other electronic device at a second heating temperature higher than the first heating temperature, and surrounded by the sealing insulating film.

Light signal processing system

A semiconductor device substrate has fine terminals with a small pitch and is able to be easily produced at a low cost without using a special process. A mounting terminal has a pyramidal shape and extending between a front surface and a back surface of a silicon substrate. An end of the mounting terminal protrudes from the back surface of the silicon substrate. A wiring layer is formed on the front surface of the silicon substrate. The wiring layer includes a conductive layer that is electrically connected to the mounting terminal.

Method of forming a device substrate and semiconductor package including a pyramid contact

In a semiconductor device circuit formation surfaces of each of a plurality of semiconductor chips can be easily located at even level when the semiconductor chips are arranged side by side so that a process of forming rearrangement wiring is simplified. The semiconductor chips are mounted on a substrate via an adhesive layer in a two-dimensional arrangement. A resin layer is formed on the substrate and located around the semiconductor elements. The resin layer has the same thickness as a thickness of the semiconductor elements. An organic insulating layer is formed over a surface of the resin layer and circuit formation surfaces of the semiconductor elements. A rearrangement wiring layer is formed on the organic insulating layer and electrodes of the semiconductor chips. External connection terminals are electrically connected to the circuit formation surfaces of the semiconductor elements through wiring in the rearrangement wiring layer.

Semiconductor device configured to be surface mountable

A structure in which a phosphorus-nickel layer, a rich phosphorus nickel layer that contains phosphorus or boron higher than this phosphorus-nickel layer, a nickel-tin ally layer, a tin-rich tin alloy layer, and a tin alloy solder layer are formed in sequence on an electrode. Accordingly, adhesiveness between a metal pattern used as the electrode, the wiring, or the pad and the solder can be improved.

External connection terminal and semiconductor device

Semiconductor device and package including forming pyramid mount protruding through silicon substrate

A semiconductor module includes a plurality of semiconductor devices each including a circuit substrate carrying thereon a single memory semiconductor chip and a socket for holding the semiconductor devices detachably.

Semiconductor module including a plurality of semiconductor devices detachably

A plurality of semiconductor chips are incorporated in a one-piece package so as to substantially increase a mounting area of a semiconductor device so that the semiconductor device can be provided with the projection electrodes having a structure which enable the semiconductor device to be mounted by a conventional surface mounting technique. A redistribution layer interconnects and integrally holds the plurality of semiconductor elements. A plurality of projection electrodes are provided on the redistribution layer for surface mounting. The plurality of semiconductor chips are rendered to be different kinds so that the plurality of different kinds of semiconductor chips together provide a complete function. The plurality of semiconductor chips may be rendered to be the same kind so as to reduce a mounting area of the semiconductor chips as a whole.

Semiconductor device having a plurality of semiconductor elements interconnected by a redistribution layer

A method of manufacturing a semiconductor device is provided. The method comprises a wire-forming step of forming a wiring on a substrate having an electrode pad so as to connect the electrode pad to a mounting terminal. The wire-forming step includes the steps of: applying a metal foil to the substrate by providing an adhesive therebetween; patterning the metal foil into a predetermined pattern so as to form the wiring; and connecting the wiring to the electrode pad electrically.

Growing community of inventors

Kawasaki, Japan

Mitsutaka Sato