Renesas Technology Corp.

Other

Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Engineering Company, Limited

Mitsutaka Niiro

Tsukasa Ooishi

Hideto Hidaka

Hiroshi Kato

Shigeki Tomishima

Hiroaki Tanizaki

Takaharu Tsuji

Masatoshi Ishikawa

Masanao Maruta

Katsumi Dosaka

Tomoya Kawagoe

Akihisa Oishi

An internal power supply potential generation circuit includes an overcharge prevention circuit connected to an internal power supply node. The overcharge prevention circuit includes a circuit outputting a signal to be determined that is determined by an internal power supply potential, a differential amplification circuit amplifying a difference in potential between the signal to be determined and a reference potential for output to a node as a signal indicating that current should be drawn, and a current draw circuit drawing current from the internal power supply node in response to the signal indicating that current should be drawn. Thus the semiconductor integrated circuit device of interest can provide a steady internal power supply potential.

Semiconductor integrated circuit device with internal power supply potential generation circuit

A semiconductor device includes an internal circuit carrying out a predetermined process in accordance with an input signal, and a comparison circuit comparing the time required for an output signal in accordance with a predetermined process to be output and an input signal propagation time of an electric line having a line length adjusted to transmit a signal in a desired time

Semiconductor device that can measure timing difference between input and output signals

A timing adjusting circuit is mounted on a semiconductor device. A reference signal TREFIN and signals TPa to TPx to be adjusted are supplied from a tester via transmission lines on a test jig. By gradually advancing phases of the signals TPa to TPx with respect to a trigger signal TRIG generated on the basis of the reference signal, the differences of transition timings of driver waveforms are held in a plurality of registers corresponding to the transmission lines. The data held by the plurality of registers is sent to the tester via a storage result outputting circuit. On the basis of the data, output timings of the driver waveforms can be adjusted by the tester with high accuracy.

Semiconductor device capable of adjusting timing of input waveform by tester with high accuracy

Switching is made between applied voltages to fuse elements H to H in a program circuit in response to a test signal /TE. To be concrete, in a test mode, a stepped-up voltage Vpp higher than a power supply voltage Vcc applied in the normal mode is applied to a fuse element to be disconnected to remove a disconnection defect left in the fuse element, thereby enabling perfect disconnection of the fuse element.

Semiconductor device removing disconnection defect in fuse element of its program circuit to stably perform coincidence comparison operation

First and second memory banks are provided with M memory blocks each having first and second memory regions, M representing an even number of no less than two, and (M&plus;1) sense amplifier bands arranged on opposite sides of each memory block, and have first and second select lines arranged therefor to select the first and second memory regions, respectively, the first select line being connected to an odd-numbered sense amplifier band of the first memory bank and an even-numbered sense amplifier band of the second memory bank, the second select line being connected to an even-numbered sense amplifier band of the first memory bank and an odd-numbered sense amplifier band of the second memory bank.

Semiconductor memory device having a column select line transmitting a column select signal

A first power supply voltage is supplied to a power supply node of a sense amplifier. A bit line driver outputs a column select signal composed of a second power supply voltage to the gate terminals of N channel MOS transistors of a GIO line gate circuit. When input/output data is &lsqb; , a third power supply voltage lower than the first power supply voltage is supplied onto a global data line. In this case, with a threshold voltage of N channel MOS transistors used, a relation is established: second power supply voltage&lE;third power supply voltage&plus;threshold voltage. As a result, a leakage current can be reduced in a semiconductor memory device driven by plural power supply voltages with respective different voltage levels.

Semiconductor memory device capable of reducing leakage current flowing into substrate

A complementary address generation circuit supplies a fuse select address signal as it is at a first fuse blow and converts the fuse select address signal to a complementary address and supplies the complementary address as an output at a second fuse blow. The output of the complementary address generation circuit is supplied to a fuse select circuit and the fuse select circuit selects a fuse group to which a substitution address is to be allocated. The fuse group used at the first fuse blow is selected in ascending order and at the second fuse blow the fuse group is selected in descending order. Thus, the spare used at the first fuse blow will be prevented from being used again in the second fuse blow and a repairable semiconductor memory device will not be rendered defective.

Semiconductor memory device preventing repeated use of spare memory cell and repairable by cell substitution up to two times

A semiconductor device having an alignment mark which is improved to enable accurate recognition of the alignment mark is provided. A first interconnection layer is provided on a semiconductor substrate. A second interconnection layer is provided on an interlayer insulating film so that first and second interconnection layers cross each other with interlayer insulating film therebetween. A surface of second interconnection layer includes, in a region where first and second interconnection layers cross each other, a flat portion which reflects laser beam vertically and upwardly and a portion including concaves and convexes which reflects laser beam irregularly, which together form an alignment mark.

Growing community of inventors

Hyogo, Japan

Mitsutaka Niiro