Nec Corporation

Nippon Electric Co., Ltd.

Mitsutaka Morimoto

Hidekazu Okabayashi

Eiji Nagasawa

Takahiko Watanabe

Toshio Takeshima

Kohei Higuchi

Yuji Okuto

Disclosed herein is an active matrix array substrate for a liquid-crystal display device including a plurality of gate and drain buses, a plurality of gate and drain terminals respectively connected to the gate and drain buses, and a plurality of slits each formed between the adjacent ones of the gate terminals and of the drain terminals to cut undesirable conductive-portions which short-circuit the adjacent two terminals.

Liquid-crystal display device having slits formed between terminals or

A dynamic memory device having a plurality of one-transistor type memory cells is disclosed. The memory device has a plurality of pillar-like semiconductor protrusions. The transfer gate transistor of a memory cell is formed along the upper portion of the pillar-like semiconductor protrusion such that its channel region is positioned at a side surface of the upper portion, and the storage capacitor of the memory cell is formed along the lower portion of the pillar-like semiconductor protrusion.

Dynamic random access memory device having a plurality of one-transistor

The present invention relates to a method of forming a diffused region with a shallow junction having a refractory metal silicide layer thereon. At first, the refractory metal silicide layer is selectively formed on a silicon substrate of one conductivity type. An insulating film is then formed at least on the refractory metal silicide layer, and a contact hole is opened on a part of the silicide layer. After necessary high temperature treatments have been conducted, a dopant impurity of the opposite conductivity type is introduced from the contact hole to the silicide layer. The impurity is laterally dispersed in the silicide layer and diffused into the whole portion of the silicon substrate in contact with the silicide layer, whereby the diffused region with a shallow junction can be formed.

Method of manufacturing semiconductor device

A process of forming electrodes and interconnections in a silicon semiconductor device comprises the steps of forming an insulating film on a silicon substrate, defining an opening in the insulating film, depositing a layer of metal having a high melting point on the insulating film, implanting ions to mix an interface between the metal layer and the silicon substrate, heating the construction in a temperature in the range of from 400 to 650 degrees Celsius to form a silicide of the metal layer in the opening, and selectively etching away an unreacted metal layer so as to self-align the silicide metal layer with the opening. The silicide metal layer is then annealed in a non-reducing gas atmosphere at a temperature ranging from 800 to 1,100 degrees Celsius.

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Tokyo, Japan

Mitsutaka Morimoto