Fujitsu Corporation

Mitsutaka Ikeda

Akira Takashima

Takao Nishimura

Kaname Ozawa

Yuji Akashi

Yoshihiro Tsukidate

Katsuhito Kikuma

Koji Yamashita

Tsutomu Nakai

Tadashi Uno

Hiroshi Onodera

Yoshikazu Homma

Fumihiko Ando

Hayato Okuda

Tsutomu Taniguchi

Toshiyuki Kurita

In a stacked semiconductor device which has a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a flexible printed wiring board provided with external connecting terminals. A printed circuit board is placed and mounted on the first semiconductor chip by flip-chip bonding. A second semiconductor chip is secured onto the printed circuit board. The second semiconductor chip is connected to the flexible printed wiring board by wire bonding. The first semiconductor chip is connected to the flexible printed wiring board by wire bonding via the printed circuit board.

Stacked semiconductor device and method of producing the same

A memory circuit capable of salvaging defective cells, comprises a plurality of memory blocks each having a plurality of memory cells, a region which stores a block address of defective memory block that has defective cell, and a comparator circuit which compares the block address that is an object of access with the block address of the defective memory block, and detects access to the defective memory block, wherein in case where the comparator circuit detects access to the defective memory block, this defective memory block is replaced by the memory block that has the uppermost address (or lowermost address) among the plurality of memory blocks. In case where a plurality of defective memory blocks are present, the defective memory blocks are replaced with substitutive memory blocks having block addresses in order from the uppermost bit (or lowermost bit).

Memory circuit having block address switching function

According to the present invention, access to a password area in a nonvolatile memory cannot be granted by simple supply of an address in a normal order. According to one preferable mode, for instance, a trap address is set in the password area so that reading information from the password area is permitted only when the password area is accessed without accessing the trap address, whereas when the password area is accessed the trap address, whereas when the password area is access through the trap address, information reading is inhibited, or meaningless data is output or the information in the password area is destroyed. This invention can make it harder to gain access to a password area which is used to protect against illegitimate copying and can provide a nonvolatile memory having a stronger copy protection capability.

Nonvolatile memory with illegitimate read preventing capability

According to the present invention, access to a password area in a nonvolatile memory cannot be granted by simple supply of an address in a normal order. According to one preferable mode, for instance, a trap address is set in the password area so that reading information from the password area is permitted only when the password area is accessed without accessing the trap address, whereas when the password area is accessed through the trap address, information reading is inhibited, or meaningless data is output or the information in the password area is destroyed. According to another preferable mode, the order in which access is made to the password area can arbitrarily be set so that accessing the password area in this order alone can permit the password area to be read, whereas when access to the password area is made in a different order, information reading is inhibited, or meaningless data is output or the information in the password area is destroyed. According to both modes, while the recording medium where the trap address or accessing order information is stored is a nonvolatile memory, it is constructed in such a manner that writing and reading are both prohibited. This invention can make it harder to gain access to a password area which is used to protect against illegitimate copying and can provide a nonvolatile memory having a stronger copy protection capability.

A semiconductor memory device comprises a detecting unit and a testing unit. The detecting unit detects a plurality of times a state of a predetermined terminal when the power is switched on, and activates the testing unit when all results of the detections show expected values. The device shifts to a connection testing mode by activation of the testing unit, and performs predetermined testing. Therefore, the testing can be performed by causing the device to shift to the testing mode without using terminals dedicated to testing. Besides, a shift to the connection testing mode by activation due to an erroneous operation or power-supply noise is prevented from occurring. In another semiconductor memory device the conversion circuit receives parallel testing patterns via a plurality of input terminals and converts the patterns into serial output patterns. Since the parallel testing patterns are converted into serial output patterns, connection testing can be performed even when the number of output terminals is small. Furthermore, another semiconductor memory device comprises an operation circuit and a conversion circuit. The operation circuit receives parallel testing patterns via a plurality of input terminals, performs a logic operation, and outputs parallel operation result patterns. The conversion circuit receives the parallel operation result patterns and converts the patterns into serial output patterns. The converted output patterns are sequentially output from output terminals. The testing patterns fed to the conversion circuit by the operation circuit can be reduced. Accordingly, the output patterns become shorter, and testing time is reduced.

Semiconductor memory device, circuit board mounted with semiconductor memory device, and method for testing interconnection between a semiconductor memory device with a circuit board

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Kawasaki, Japan

Mitsutaka Ikeda