Fujitsu Corporation

Fujitsu Semiconductor Limited

Mitsuru Tomono

Katsuhiro Yoda

Takahiro Notsu

Makiko Ito

Hiroaki Yoshida

Satoshi Tanabe

Ryosuke Yamanaka

Naomi Hadatsuki

Kodai Moritaka

Teruo Ishihara

Makoto Hamaminato

Naoto Yoneda

Hiroya Uehara

Hiroshi Michishita

Soseki Aniya

A joint position estimation device including a memory, and a processor connected to the memory. The processor executes a process including estimating, by a first DNN for which a first parameter determined by learning of the first DNN has been set, a body part region of the animal with respect to input image to be processed; and estimating, by the second DNN for which a second parameter determined by learning of the second DNN has been set, a first joint position and a second joint position in each of the body part region estimated by the first DNN and a plural body parts region in which a plurality of the body part regions are connected.

Joint position estimation device, joint position estimation method, and joint position estimation program

An operation processing device includes: a memory; and a processor coupled to the memory and configured to: acquire statistical information on distribution of bits in fixed point number data after execution of an instruction on the fixed point number data; and update a decimal point position of the fixed point number data.

Operation processing device, information processing device, and information processing method

An apparatus for data output control includes: an encryption executing circuit configured to receive first data from a processor with a control signal indicating whether the first data is to be encrypted, and encrypt the first data when the control signal indicates that the first data is to be encrypted; a selection circuit configured to output any of the encrypted first data and second data; and an output control unit configured to set a frequency of second timing to be smaller than a frequency of first timing, and transmit a signal to the selection circuit instructing that the second data be outputted at the second timing, in a case where the second data is received from the processor.

Data output control apparatus, information processing apparatus, and data output control method

An operation processing apparatus includes a memory and a processor coupled to the memory. The processor executes an operation according to an operation instruction, acquires statistical information for a distribution of bits in fixed point data after an execution of an operation for the fixed point data according to an acquisition instruction, and outputs the statistical information to a register designated by the acquisition instruction.

Operation processing apparatus, information processing apparatus and information processing method

A simulation method performed by a computer for simulating operations by a plurality of cores based on resource access operation descriptions on the plurality of cores, the method includes steps of: extracting a resource access operation description on at least one core of the plurality of cores by executing simulation for the one core; and, under a condition where the one core and a second core among the plurality of cores have a specific relation in execution processing, generating a resource access operation description on the second core from the resource access operation description on the one core by reflecting an address difference between an address of a resource to which the one core accesses and an address of a resource to which the second core accesses.

Simulation program, method, and device

A non-transitory computer-readable recording medium having stored therein an information processing program for causing a computer to execute a process includes: calculating, by using an image including an object having a plurality of joints and having a plurality of frames consecutive in time, a probability distribution of a joint position of the object in each frame; calculating a transition score by evaluating a consistency of a transition of a joint of the plurality of joints using transition information of the joint among different frames; and estimating a pose of the object from a score of the probability distribution and the transition score.

Information processing apparatus, information processing method, and information processing system

An information processing device includes: a memory; and a processor coupled to the memory and configured to: estimate a first position of a first joint in a two-dimensional plane based on a color image, and estimate a first positional relationship between the first joint and a second joint coupled to the first joint via a portion in the two-dimensional plane; estimate a second position of the first joint in the two-dimensional plane based on a depth image indicating respective depths of the first joint and the second joint, and estimate a second positional relationship between the first joint and the second joint in a three-dimensional space; and estimate a third position of the first joint in the two-dimensional plane and posture of the portion in the three-dimensional space based on the first position, the first positional relationship the second position, and the second positional relationship.

Information processing device, information processing method, and recording medium

A processor circuit includes: multiple processor cores; multiple individual memories; multiple shared memories; multiple memory control circuits; multiple selectors; and a control core; wherein when an address of the read request from the first processor associated with a specific memory control circuit is identical to the transfer source address, the specific memory control circuit controls the transfer data based on the read request to be transferred to the transfer destination address via a specific selector of the multiple selectors in which the transfer selection information is set, wherein, when the control core sets read selection information in each of the multiple selectors, read data is read by one of the first processor core and the first adjacent processor core from the associated shared memory via a specific selector of the multiple selectors in which the read selection information is set.

Processor circuit, information processing apparatus, and operation method of processor circuit

A processor includes: a plurality of processor cores; and an internal memory configured to be accessed from the plurality of processor cores, wherein an arithmetic circuit provided in any of the plurality of processor cores includes: a plurality of first registers provided in a first stage of the arithmetic circuit, a regular addition circuit including a first adder and a second register, the first adder being configured to add a plurality of outputs of the plurality of first registers, the second register being configured to be provided in a second stage and latch an output of the first adder, an overtaking addition circuit including a second adder, the second adder being configured to add a plurality of outputs of the plurality of first registers, and a synthesis circuit including a third adder and a third register.

Processor, information processing apparatus and operation method for processor

A processor includes: a first memory configured to store image data including pixel data of a plurality of pixels that are two-dimensionally arranged; a second memory configured to store neighborhood matrix image data including pixel data of a neighborhood matrix; and a format converter that includes (a) a readout circuit configured to read out the image data from the first memory, (b) a padding arithmetic unit configured to receive the read-out image data, select pixel data of the received read-out image data and padding data inserted at periphery of the plurality of pixels in accordance with mask values of a padding mask, and generate the neighborhood matrix image data including the pixel data and the padding data, and (c) a writing circuit configured to write the neighborhood matrix image data to the second memory.

Processor, information processing apparatus, and operation method of processor

A processor accesses memory storing a compressed instruction sequence that includes compression information indicating that an instruction that with respect to the preceding instruction, has identical operation code and operand continuity is compressed. The processor includes a fetcher that fetches a bit string from the memory and determines whether the bit string is a non-compressed instruction, where if so, transfers the given bit string and if not, transfers the compression information; and a decoder that upon receiving the non-compressed instruction, holds in a buffer, instruction code and an operand pattern of the non-compressed instruction and executes processing to set to an initial value, the value of an instruction counter that indicates a count of consecutive instructions having identical operation code and operand continuity, and upon receiving the compression information, restores the instruction code based on the instruction code held in the buffer, the instruction counter value, and the operand pattern.

Compressing detected current and preceding instructions with the same operation code and operand patterns

A system of altering an audio signal presented to a user may include an input configured to receive data indicating a status of an environment outside of an audio device, where the audio device is configured to present an audio signal to a user. The system may also include a detection unit configured to detect a condition based on the received data and an audio altering unit configured to direct altering of the audio signal presented to the user based on the detection of the condition.

Altering audio signals

Aspects may include a method of designing a system-on-chip. The method may include receiving multiple processing modules, each representing in software one of multiple processing units of a system-on-chip. The method may further include modeling communications from one or more of the multiple processing modules as accesses to memory. The method may further include generating a coherent memory module associated with the multiple processing modules based on modeling the communications from the one or more of the multiple processing modules as accesses to memory. The coherent memory module may represent in software a coherent memory associated with the multiple processing units.

System-on-chip design structure

An example embodiment includes a distributed file management system. The distributed file management system includes a central storage device that is communicatively coupled to data repositories configured to store one or more files. The central storage device includes a processor and a tangible computer-readable storage medium. The tangible computer-readable storage medium is communicatively coupled to the processor and has computer-executable instructions stored thereon that are executable by the processor to perform operations. The operations include receiving file access requests from the data repositories. The operations also include transmitting location information of files requested in the file access requests. The location information includes internet protocol (IP) addresses of the data repositories on which the files are stored. The operations also include receiving updated file indices from the data repositories indicating remote access to files and updating a central access log and a central file index to include the updated file indices.

Virtual storage gate system

A system of automatically changing a viewing angle of a display device based on a determination of content confidentiality includes a display device, an auditing application, and a privacy filter control. The auditing application is configured to analyze content to be displayed on the display device for confidentiality indicators. The privacy filter control is configured to automatically change a current viewing angle of the display device from a first viewing angle to a second viewing angle that is less than the first viewing angle when the content includes at least one confidentiality indicator and the current viewing angle of the display device is the first viewing angle.

Growing community of inventors

Higashimurayama, Japan

Mitsuru Tomono