Sony Corporation

Ezaki Glico Co., Ltd.

Kanto Natural Gas Development Co., Ltd.

Omikenshi Co., Ltd.

Mitsuru Taguchi

Naoki Komai

Keiichi Maeda

Takeshi Nogami

Hideyuki Kito

Koji Miyata

Shingo Kadomura

Toshiaki Hasegawa

Hirofumi Sumi

Kazuhide Koyama

Takaaki Miyamoto

Teruo Hirayama

Kazuhiro Hoshino

Takeshi Takaha

Akira Yoshio

Yukiyasu Sugano

Hidenori Kenmotsu

Yoshinobu Terada

Osamu Inoue

Yasuhiro Chiba

Katsumi Ando

Haruyo Sambe

Masatoshi Yoshikawa

Hiroshi Suzawa

Mieko Takaku

Miyata Koji

Tatsuo Kaiho

A method for producing an amylose-containing rayon fiber, comprising the steps of: mixing an aqueous alkaline solution of amylose with viscose to obtain a mixed liquid, spinning the mixed liquid to obtain an amylose-containing rayon fiber, and bringing the amylose-containing rayon fiber into contact with iodine or polyiodide ions, thereby allowing an amylose in the amylose-containing rayon fiber to make a clathrate including the iodine or polyiodide ions, wherein the amylose is an enzymatically synthesized amylose having a weight average molecular weight of 3&#xd7;10or more and 2&#xd7;10or less. A method for collecting iodine from brackish water with high efficiency utilizing the amylase-containing rayon fibers.

Iodine- and amylose-containing fibers, method for production thereof, and use thereof

A process for producing a semiconductor device for forming a highly reliable wiring structure is provided that solves the problem occurring on using a xerogel or a fluorine resin in an inter level dielectric between the wirings to decrease a wiring capacitance, and the problem occurring on misalignment. A process for producing a semiconductor device comprising an inter level dielectric containing a xerogel film or a fluorine resin film comprises a step of forming, on the inter level dielectric comprising a lower layer of the inter level dielectric formed with an organic film and an upper layer of the inter level dielectric formed with a xerogel film or a fluorine resin film, a first mask to be an etching mask for forming a via contact hole by etching the inter level dielectric, and a step of forming, on the first mask, a second mask, which comprises a different material from the first mask, to be an etching mask for forming a wiring groove by etching the inter level dielectric.

Process for producing semiconductor device

A semiconductor device capable of suppressing diffusion of copper at an interface between a copper wire and a cap film to enhance an electromigration resistance to ensure reliability of the copper wire, and a manufacturing method thereof are provided. The semiconductor device according to the present invention comprises an insulating film () formed on a substrate (), a concave portion () (for example, a groove) formed in the insulating film, a conductive layer () embedded in the concave portion through a barrier layer (), and a cobalt tungsten phosphorus coating () to connect with the barrier layer on the side of the conductive layer and to coat the conductive layer on the opening side of the concave portion.

Semiconductor device having a conductive layer with a cobalt tungsten phosphorus coating and a manufacturing method thereof

An electrolytic polishing apparatus for electrolytic-polishing a conductive film subject to formed on a substrate including a resistance measuring unit for measuring the resistance of the film. The electrolytic polishing apparatus may also include a termination point detecting portion for detecting a termination point of polishing by reading a variation of the resistance value measured by the resistance measuring unit, or a polishing control portion for terminating electrolytic polishing on the basis of the termination point of polishing detected by the termination point detecting portion.

Electrolytic polishing apparatus, electrolytic polishing method and wafer subject to polishing

A method of implementing an electrolytic polishing process against a wiring-material film by way of preventing excessive polishing or incomplete polishing caused by presence of differential steps locally generated in the objective wiring-material film. The inventive method comprises a step of forming a wiring-material film for burying recessed portions formed on an insulating film formed on a substrate via a plating process; a step of reducing a local differential step generated on the surface of the wiring-material film by way of preserving the wiring material film on the insulating film; and a final step of removing the wiring-material film deposited on the insulating film by way of preserving such wiring-material film deposited, solely inside of the recessed portions.

Method of manufacturing a semiconductor device

A process for fabricating a semiconductor device, which comprises forming a recess portion in an insulating film covering a wiring made of copper or a copper alloy so that the recess portion reaches the wiring, wherein, after forming the recess portion, a plasma treatment using a gas containing hydrogen gas and nitrogen gas is conducted in a state such that the wiring is exposed through the bottom portion of the recess portion, or a plasma treatment using a gas containing hydrogen gas is conducted in a state such that the wiring is exposed through the bottom portion of the recess portion while cooling a substrate on which the wiring is formed. By the process of the present invention, a problem of redeposition of copper on the sidewall of a via hole in the argon sputtering and a problem of an etching process of the organic insulating film in the hydrogen plasma treatment can be solved, thus realizing excellent cleaning of the bottom portion of the via hole.

Process for fabricating a semiconductor device having recess portion

The present invention is to provide a method for fabricating semiconductor devices capable of eliminating a height difference on a base member caused by a residual plating seed layer remained in a portion where an electrode comes into contact and is thus prevented from contacting with an electrolytic polishing fluid, where such height difference has been a problem in introducing the electrolytic polishing process into wafer process. The method comprises the steps of forming a plating seed layer on the base member; forming by the plating process a plated film on the plating seed layer in an area excluding the outer peripheral portion of the base member; polishing the plated film together with the plating seed layer by the electrolytic polishing process; and selectively removing the plating seed layer remaining on the outer peripheral portion of the base member.

Method for fabricating semiconductor devices

The object of the invention is to solve failure in embedding conductive material by electroplating caused because organic insulating material is deformed by the compressive stress of a barrier metal layer such as tantalum nitride used for grooved interconnection, a groove-used for grooved interconnection is deformed and a seed layer is not fully formed in the groove and to enhance reliability upon interconnection. To achieve the object, a semiconductor device according to the invention is based upon a semiconductor device having a groove formed through a second insulating film over a substrate, a barrier metal layer formed at least on the inner wall of the groove and grooved interconnection embedded inside the groove via the barrier metal layer and is characterized in that a concave portion is continuously or intermittently formed along a groove through a second insulating film within a predetermined interval from grooved interconnection.

Semiconductor device and its manufacturing method

In a related interconnection structure that is formed by filling a metal, there have been problems, since defective connection occurs due to generation of voids and other features caused by poor filling of the metal, which entails reduction in reliability, and contact resistance is large due to a barrier metal layer at a contact portion. A novel interconnection structure is provided which comprises: a recess (for example, a contact hole, a trench, or a trench and a contact hole formed at a bottom of the trench), which is connected onto a conductive material mass formed in an insulating film, and which is formed in the insulating film; a barrier metal layer formed on side walls of the recess; and metal material masses filled in the interior of the recess, wherein the metal material masses are formed with a metal repeatedly filled into the recess over a plurality of times, and a metal material mass and a conductive material mass are directly connected to each other.

Interconnection structure and fabrication process therefor

Disclosed is a magnetron sputtering system enabling formation of a film of a ferroelectric substance by suppressing occurrence of a magnetic field due to an eddy current. The magnetron sputtering system includes a flat target; magnetic field applying means (magnets), provided in the vicinity of a back surface of the target, for applying a magnetic field to a front surface of the target; and magnetic field rotating means (motor) for rotating the magnetic field applying means so as to rotate the magnetic field applied to the front surface of the target. The magnetic field rotating means is provided with rotational speed varying means (speed controller) for varying the rotational speed of the magnetic field applied by the magnetic field rotating means.

Method for fabricating a semiconductor device in a magnetron sputtering system

A manufacturing method for forming a dual damascene structure in which the effective permittivity of an inter-layer insulating film is lowered without an etching mask for forming a contact hole, which is otherwise formed in the inter-layer insulating film. The manufacturing method comprises the step of forming an inorganic film to serve as an etching mask, on the inter-layer insulating film; the step of forming a first opening pattern for forming a wiring groove, in an upper part of the inorganic film; and the step of forming a second opening pattern for forming a contact hole, so as to coincide with the first opening pattern at least partially. Further, the contact hole is formed in the inter-layer insulating film by employing an etching mask made of the inorganic film, the inorganic film is etched into a state where only a third opening pattern obtained by transferring the first opening pattern is formed, and a wiring groove is formed in the inter-layer insulating film by employing the resulting inorganic film as the etching mask.

A hard Al oxide film having a high melting point, which grows on the surface of an Al&mdash;Cu film during a wafer is carried in atmospheric air, obstructs the burying of a viahole with the Al&mdash;Cu film by high pressure reflow, with a result that a void remains in the hole. The present invention is intended to remove such an Al oxide film grown on the Al&mdash;Cu film formed by sputtering, by Ar,sputtering/etching directly before high pressure reflow. Moreover, when a Ti oxide film is present on the surface of a Ti based underlying film formed by CVD, an Al oxide film is possibly grown at the boundary between the Ti based underlying film and an Al&mdash;Cu film laminated thereon. In this case, the Ti oxide film is similarly removed directly before formation of the Al&mdash;Cu film, thereby preventing the growth of the Al oxide film. With this method, it is possible to highly keep thermal flow of a conductive film in a high pressure reflow process, and hence to desirably bury a connection hole with the conductive film.

Method of manufacturing semiconductor device

A method of forming wirings which comprises forming a film of a silicon-containing metal layer at a high temperature on an underlying metals, thereby forming a silicon alloy layer comprising the underlying metal and the silicon-containing metal during film formation. In a case of forming wirings by a silicon-containing metal layer occurrence of Si nodules can be eliminated to obtain wirings of high reliability.

Method of forming wirings

A metallization method for filling an Al-based material in a contact hole having a barrier metal structure, in which high barrier characteristics and high step coverage may be achieved simultaneously, is proposed. The present invention is based on two concepts. The first concept is to provide a Ti/TiON/Ti three-layer barrier metal structure and to deposit a layer of the Al-based material by high temperature sputtering. Sufficient barrier characteristics may be provided by the intermediate TiON layer of the three-layer structure. The interface between the Al-based layer and the barrier metal layer is the Ti layer having excellent wetting characteristics with respect to the Al-based layer so that the contact hole can be filled uniformly without forming voids. The second concept is to set the substrate heating temperature during high temperature sputtering to 450 to 550&deg; C. and to set the deposition rate to 0.6 &mgr;m/minute or less. In this manner, moderate Al migration and sufficiently long reaction time may be assured even on a Ti layer which partially reflects the rough surface morphology of the TiON layer for further improving reliability in filling.

Growing community of inventors

Tokyo, Japan

Mitsuru Taguchi