Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Mitsubishi Electric Semiconductor Software Co., Ltd

Mitsubishi Electric Semiconductor Software Corporation

Mitsuru Sugita

Toyokatsu Nakajima

Toshihiro Abe

Yoshio Kasai

Naoki Ootani

Takashi Miyake

Hiroyuki Hashimoto

Kikuo Muramatsu

Hideo Inoue

Tatsuya Imakura

Kazuyuki Iwaguro

Yurika Sumida

A microcomputer with a built-in flash memory is obtained in which the flash memory can be properly rewritten with a rewrite program kept placed on the flash memory and without requiring additional complicated control circuitry. On accepting an erase/write command which constitutes a rewrite command, a flash memory module () outputs to a flash memory control circuit () a ready status signal RYIBY indicative of a busy state during execution of the series of processing. When the ready status signal RYIBY indicates the busy state, the flash memory control circuit () outputs a hold signal HOLD at active 'H,' in order to inhibit a CPU () from accessing the flash memory module (). When the ready status signal RYIBY has recovered the ready state, the flash memory control circuit () outputs the hold signal HOLD at 'L' to allow the CPU () to access the flash memory module ().

Microcomputer including a flash memory and a flash memory rewrite program stored therein

Redundant circuits to are provided in correspondence to memory blocks to , respectively. Bit lines BL to BL are located across the memory blocks. Spare bit lines SBL and SBL are located across the redundant circuits to . When a memory cell failure occurs in the memory block except a predetermined memory block (for example, a boot block) and when the bit line BL corresponding to the memory cell failure is replaced with the spare bit line SBL , each of switches and is put into an on state in correspondence to the spare bit line SBL . Furthermore, each of switches and is put into the on state in correspondence to the bit line BL . As a result, the spare bit line SBL turns the redundant circuit corresponding to the memory block , to be connected to the memory block

Flash memory having enhanced yield and having enhanced reliability in redundant and dummy circuits

Defect information about a defective memory block is stored into a large capacity memory block having a low rewrite frequency and a block select circuit is provided that selects a backup memory block when the stored defect information is referred and the defective memory block is selected.

Nonvolatile semiconductor memory device with backup memory block

Analog input selection circuits comprising an input terminal, an output terminal, a transmission path extending between the input terminal and the output terminal, transmission switches that open or close the transmission path, an over-voltage protection switch which connects or does not connect the transmission path to the ground, a PMOS transistor provided between the input terminal and a power supply, and an NMOS transistor provided between the input terminal and the ground are formed on an identical semiconductor substrate. If the semiconductor substrate is P-type, then a region in which the NMOS transistor is formed is surrounded by an N-well region.

Analog input selection circuit protected from negative over-voltage

A semiconductor device of one chip has a first power supply terminal allowing connection with an external power supply IC, a second power supply terminal allowing connection with the external power supply IC, a main voltage dropping circuit connected with the first power supply terminal, a secondary voltage dropping circuit connected with the second power supply terminal, and an internal circuit connected with the main voltage dropping circuit and the secondary voltage dropping circuit. A high voltage of the external power supply IC is received in the main voltage dropping circuit through the first power supply terminal and is dropped. The high or low voltage of the external power supply IC is received in the secondary voltage dropping circuit through the second power supply terminal and is dropped. The internal circuit is operated by using the dropped voltage obtained in the main or secondary voltage dropping circuit.

Semiconductor device

A storage portion places data through a data output buffer on a data line D0.sub.P when a control line R00H becomes active, and places data through a data output buffer on a data line D0.sub.Q when a control line R03H becomes active. The storage portion further takes as input a signal on the data line D0.sub.P through a transmission gate when a control line W00H becomes active, and takes as input a signal on the data line D0.sub.Q through a transmission gate when a control line W003H becomes active. Thus, a storage device is provided to have the storage portion accessed by a plurality of access means at different addresses. It is thereby possible to select the optimal method of access to the storage portion, resulting in prevention of reduction of a program efficiency.

Multiple ports storage device with programmable overlapped data bits

An AD converting apparatus which is provided with a data update flag 3b for storing a first value ('1') when an analog signal is newly converted by an AD converter 1 to digital data and is stored into a data register 3a, and for storing a second value ('0') when the contents of the data register 3a are read out externally in a state under which the first value has been stored, and which eliminates a wasteful operation such that the data having already been used is used again to perform an arithmetic operation, by building in a hardware capable of indicating whether the data after AD conversion has already been used once or not, and thus improving processing speed as a whole; and a data processor in which the AD converting apparatus is built in.

Ad converting apparatus including holding means indicating whether or

A multiport memory includes a first memory block and a second memory block which are independently accessible with each other. Each of the first and second memory blocks can be accessed simultaneously through first and second ports. The memory includes a first access conflict detector for detecting an access conflict on the first memory block, a second access conflict detector for detecting an access conflict in the second memory block, a first arbitor responsive to the first detector for arbitrating an access conflict in the first memory block, and a second arbitor responsive to the second detector for arbitrating an access conflict in the second memory block. The memory further includes a selector for transferring the arbitration result of the first arbitor to the second memory block while neglecting the arbitration result of the second arbitor only when both the first and second detector detect the access confliction.

Multiport memory and method of arbitrating an access conflict therein

In a semiconductor device having an MPU and a plurality of peripheral devices controlled by the MPU through a bus, to facilitate the interconnection of the peripheral devices without the use of the MPU, improve response speed and the processing speed of a main program by eliminating an interrupt processing from the processings of the MPU, facilitate changes in the interconnection of the peripheral devices, and enable a reduction in the number of external terminals, event buses for transmitting event signals are provided between the peripheral devices or between the peripheral devices and the external terminals so that the connection between the peripheral devices and the external terminals can be switched by the multiplexers.

System for selecting path among plurality of paths using plurality of

A watch don timer comprising a reload register 2 and a shift register 3 is disclosed. In the case where an object to be monitored is operating normally, a circuit 43 is supplied with as a reload request signal the rising timing of a monitor signal changing cyclically, which is reloaded from the reload register 2 of the shift, register 3 in synchronism with a reload request signal in accordance with the value of data located in each bit of the shift register 3. Circuits 41, 42 are adapted to detect an abnormal condition in the case where a reload request signal is given in a cycle shorter or longer than a predetermined cycle of reloading. This configuration realizes a watch dog timer with a comparatively small scale of circuit configuration in which the pulse width of the input signal is monitored, the cycle detected and the execution of a plurality of instructions monitored, while at the same time having a programmable width and cycle and a tolerable range thereof.

Watch dog timer

A multiprocessor-type one-chip microcomputer, of the type having a plurality of processors, each having a separate address space, a plurality of programmable ROMs, for storing program data for each processor, and a set of functional terminals, with the microcomputer including a common writing bus and a control means for coupling either the common writing bus or a set of functional lines to the functional terminals based on the setting of a mode setting signal. During normal operations the functional lines are coupled to the functional terminals and each programmable ROM is accessed by a processor using addresses in the address space of the processor. When new instruction data is to be written to the programmable ROMs, the common writing bus is coupled to the functional terminals and instruction data is written to the programmable ROMs using addresses in a common address space.

Multiprocessor-type one-chip microcomputer with dual-mode functional

A timer has a function of compensation calculation and includes a compensation value register 1 for holding a compensation value and an arithmetic unit 2 which adds or subtracts a compensation value '.alpha.' held in the compensation value register 1 and a value 'CC' of a count value C of a counter 3 at that time point, and by loading the operation result of the arithmetic unit 2 to the counter 3. Such a timer reduces a burden on a CPU and is capable of compensating the count value correctly regardless of a remaining time.

Timer with a compensation value to increment or decrement a count value

A dual-port memory is interposed between a host system and a slave system in a multiprocessor system, and data transmission between the host system and the slave system is performed through the dual-port memory using first and second input/output ports, the dual-port memory being accessible from the host system and the slave system simultaneously. An address region of the dual-port memory is placed overlapping the address space of an internal memory of the host system, so that no change is needed in programming in the host system, however, data collision may be generated in a region in the address space shared by the internal memory and the dual-port memory. In order to prevent data collision, the dual-port memory includes a memory cell array having a plurality of memory cells, first cell selection circuitry and second cell selection circuitry, and read data output prohibiting circuitry which prohibits data read out from a selected memory cell from being output to the host system. The output of data read out from a portion of the memory cells in the memory array may be prohibited instead.

Dual-port memory with selective read data output prohibition

An address translating circuit is disclosed for translating a virtual address signal generated from an external CPU into a real address signal applicable to the dual-port random access memory (DPRAM) in the microcomputer. This address translating circuit includes an offset register, an enabling signal generating circuit, and a subtractor provided in the microcomputer. The offset data obtained based upon the difference between an address map handled by the external CPU and an address map handled by the internal CPU is set in the offset register. The enabling signal generating circuit is responsive to the more significant bits of the virtual address signal and the offset data to generate an enabling signal. The subtractor is responsive to the intermediate bits of the virtual address signal and the offset data to generate a translated address signal. Since the address translation is performed by circuit operation without depending on the processing of the external CPU, the burden on the external CPU is reduced

Address translating apparatus for translating virtual address into real

A multi-port RAM has a decoding portion for decoding a plurality of specific addresses for generating interruptions and a selection circuit for selecting some addresses from among the plurality of specific addresses. Since the plurality of addresses are selected for generating interruptions in parallel or in the sequence of time for each generation of an interruption, the data processing capability at the time of generation of interruptions can be improved.

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Hyogo, Japan

Mitsuru Sugita