Nec Corporation

Konica Minolta Medical and Graphic, Inc.

Konica Minolta, Inc.

Konica Minolta Business Technologies, Inc.

Mitsuru Sekiguchi

Masashi Kondo

Takehiko Shoji

Yasushi Nagata

Narito Goto

Hisatake Okada

Takeshi Isoda

Kazuya Tsukada

Kazuhisa Ninomiya

Ryosuke Fujio

Yutaka Hatanaka

Yoshikazu Kurihara

Provided are: a probe reagent which is capable of stably yielding a fluorescence signal in FISH while inhibiting non-specific adsorption by the use of a nucleic acid molecule having a smaller number of bases than a BAC probe; and FISH using the probe reagent. The probe reagent is for in situ hybridization and comprises: phosphor-integrated nanoparticles containing phosphors integrated therein; and a nucleic acid molecule having a prescribed nucleic acid sequence, which phosphor-integrated nanoparticles and nucleic acid molecule are bound with each other.

Probe reagent and fish using probe reagent

A radiation detector of a compact size and producing almost no image defect is disclosed, comprising a first radiation-transmissive substrate, a first adhesive layer, a second radiation-transmissive substrate, a scintillator layer and an output substrate provided with a photoelectric conversion element layer which are provided sequentially in this order, wherein an arrangement region of the scintillator layer in a planar direction of the layer includes an arrangement region of the photoelectric conversion element layer in a planar direction of the layer and an arrangement region of the first substrate in a planar direction of the substrate, and the arrangement region of the first substrate includes the arrangement region of the photoelectric conversion element layer; and when the arrangement region of the scintillator layer is divided to plural areas, a coefficient of variation of filling factor is 20% or less which is defined as a standard deviation of filling factor of phosphor of the plural areas, divided by an average value of the filling factor.

Radiation detector

A semiconductor nanoparticle and semiconductor nanorod that have optical characteristics (luminescence intensity and emission lifetime) superior to those of conventional core/shell nanosized semiconductors. There are provided a triple-layer semiconductor nanoparticle, and triple-layer semiconductor nanorod, having an average particle diameter of 2 to 50 nm and comprising a core layer, an interlayer and a shell layer, wherein the layers are composed of different crystals, and wherein the crystal constructing the shell layer exhibits a band gap greater than that of the crystal constructing the core layer, and wherein the crystal constructing the interlayer has a lattice constant assuming a value between those of the crystal constructing the core layer and the crystal constructing the shell layer.

Triple-layer semiconductor nanoparticle and triple-layer semiconductor nanorod

A scintillator panel comprising: a radiation-transparent substrate; and a phosphor layer provided on the substrate, the phosphor layer emitting light when irradiated with a radiation, wherein at least one edge of the substrate and at least one edge of the phosphor layer are arranged on a same plane.

Scintillator panel, method of manufacturing the same and radiation imaging apparatus

An objective is to provide a flat panel detector exhibiting high durability and less noise, which is fitted with a scintillator for radiation exhibiting high emission efficiency, wherein the scintillator is easy to be manufactured because of the simple structure. Also disclosed is a scintillator panel for radiation possessing a radiotransparent substrate and provided thereon, a phosphor layer from which light is emitted by exposing the substrate to radiation and a reflective film at which light from the phosphor layer is reflected, wherein the reflective film provided between the substrate and the phosphor layer possesses a multilayer film composed of at least two dielectric layers exhibiting a high reflectivity.

Scintillator panel for radiation, and flat panel detector

A radiation flat panel detector is created in which degradation of a phosphor layer property during aging is inhibited, the phosphor layer is protected from chemical alteration and physical impact, and sharpness is excellent. A flat panel detector possessing a light-receiving element and provided thereon, a scintillator panel possessing a scintillator sheet having a phosphor layer provided on a substrate and provided thereon, a first protective film placed on the phosphor layer side and a second protective film placed on the substrate side to seal the scintillator sheet, wherein the light-receiving element is provided on the first protective film side of the scintillator panel; the scintillator sheet is sealed at 5-8000 Pa; and the phosphor layer brought into contact with the first protective film and the light-receiving element plane brought into contact with the first protective film both have a surface roughness Ra of 0.05-0.8 &#x3bc;m.

Flat panel detector

A scintillator plate comprising: (i) a radiation transmissive substrate; (ii) a light absorbing layer formed on the substrate, the light absorbing layer absorbing light of a prescribed wavelength range; and (iii) a scintillator layer formed on the light absorbing layer, the scintillator layer converting radiation to the light having a wavelength absorbable to the light absorbing layer.

Scintillator plate, manufacturing method of the same and radiation image sensor

An objective is to provide a scintillator panel by which a converted light signal can be efficiently transmitted to suitably realize an FPD exhibiting a high radiation-to-light conversion efficiency. Also provided is a scintillator panel possessing a substrate and provided thereon, a phosphor layer possessing columnar crystals made of cesium iodide, wherein a columnar crystal tip angle is 40-80&#xb0;. Further, the above-described phosphor is preferably formed via vacuum evaporation.

Scintillator panel

A nonvolatile semiconductor memory device comprises a plurality of sectors each having a plurality of memory cell arrays, a controller which responds to an address signal and a control signal to activate at least one of the sectors; and a plurality of data comparing circuits provided in the memory cell arrays, respectively, the data comparing circuits each which latches a write data to be written the respective memory cell arrays and compares the write data latched and a data read out from the respective memory cell arrays to produce a comparison result. The controller activates all of the sectors when the control signal has a first logic level regardless of levels of the address signal so that write data is written into the memory cell arrays of the sectors activated. The controller activates the sectors in sequence in response to changing levels of the address signal when the control signal has a second logic level to output the comparison results from the data comparing circuits in sequence.

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device has writing signal line selecting transistors for applying writing signals to memory elements, respectively, reading signal line selecting transistors for delivering reading signals from the memory elements, respectively, and bit line selecting transistors connected between the writing signal line selecting transistors or the reading signal line selecting transistors and the memory elements, for selecting bit lines of each of the memory elements.

It is an object of the invention to provided an electrically erasable and programmable non-volatile semiconductor memory device, in which misread of a datum stored in a memory cell can be avoided by suppressing floating of the potentials of a memory cell source wire and a word wire in case that the operation of the memory device shifts from erasing pulse application to erase verify. Two transistors with different current-driving capabilities are connected in parallel and inserted between the memory cell source wire and the ground plane. When the operation of the memory device shifts from erasing pulse application to erase verify, a N-type transistor with lower current-driving capability turns on at fist, thereby the potential of the memory cell source wire is slowly reduced, and the other transistor with higher current-driving capability turns on afterward. After the memory cell source wire is connected with the ground plane and its potential is perfectly stabilized, the datum stored in the memory cell can be normally read.

Non-volatile semiconductor memory device

In a semiconductor memory device comprising a plurality of memory arrays, the memory array is given a predetermined potential from a terminal via a reference line. Further, a plurality of source switches are connected to the memory arrays and the reference line. The source switches selectively transfer the predetermined potential to each of the memory arrays. In this case, each of the source switches includes a transistor having an electrical ability which is determined by a length of the reference line between each source switch and the terminal. When the transistor is formed by a MOS transistor, the above electrical ability is specified by the ON resistance of the MOS transistor. The MOS transistors are designed so that the ON resistance becomes lower as the length of the reference line between the source switch and the terminal becomes longer. At any rate, a substantially constant voltage is supplied to each of the memory arrays irrelevant of the length of the reference line between each source switch and the terminal.

Semiconductor memory device having reduced variation of erasing and

In a method of initializing a flash EEPROM, a pre-programming operation of a predetermined data is first performed in a plurality of memory cells of a memory cell array and then an erasing operation is performed to the plurality of memory cells. Then, a verifying operation of whether the erasing operation is correctly performed is performed. During an initializing operation composed of the pre-programming operation, the erasing operation and the verifying operation, electrons or holes trapped in a tunnel oxide film are pulled out.

Non-volatile semiconductor memory device having trapped charges pulled

When floating gate type memory transistors undesirably enter into an over-erased state, a diagnostic potential generator supplies a first diagnostic potential to a source line and second and third diagnostic potentials to non-selected word lines and a selected word line; the potential difference between the first diagnostic potential and the second diagnostic potential causes an over-erased memory transistor to be turned off, and the potential difference between the first diagnostic potential and the third diagnostic potential allows an over-erased memory transistor to turn on so as to identify each over-erased memory transistor by its row and column addresses.

Growing community of inventors

Tokyo, Japan

Mitsuru Sekiguchi