Fujitsu Corporation

Mitsuru Satou

Miki Takagi

Takeo Nakamura

Terunobu Maruyama

Hiroji Takeyama

Yuki Kumon

The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing sectionperforms structural matching so as to determine whether there are portions corresponding in circuit structure to each other in corresponding logic cones of the two circuits. An internal DBrecords the results of the structural matching as an identifier for each element. A subcone extracting sectionextracts, as a subcone, a collection of elements, which are mutually to one another and have the same identifier, from each logic cone. A verifying sectionperforms logical equivalence verification between the two circuits for each of the extracted subcones. A display control sectiondisplays only those subcones for which the logical equivalence verification has resulted in mismatch.

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Kawasaki, Japan

Mitsuru Satou