Sharp Kabushiki Kaisha Corporation

Elpida Memory, Inc.

Mitsuru Nakura

Kazuya Ishihara

Nobuyoshi Awaya

Takashi Nakano

Shinobu Yamazaki

Takahiro Takimoto

Kazuhiro Natsuaki

Masayo Uchida

Suguru Kawabata

Daiichiro Nakashima

Yoshiji Ohta

Rieko Ogawa

Kenji Mae

Akiyoshi Seko

Junya Onishi

A maturity determination device includes an image capturing device including a plurality of pixels arrayed one-dimensionally or two-dimensionally, the image capturing device performing image capturing of at least a part of a fruit or vegetable product to acquire an image, the plurality of pixels including a plurality of first pixels each including a first light transmission filter selectively transmitting light of a first wavelength band, the intensity of the light of the first wavelength band reflected by the fruit or vegetable product varying in accordance with a maturity level; and a signal processing circuit configured to find an area size ratio of an intensity distribution of the light of the first wavelength band on the basis of a predetermined reference value based on a pixel value obtained from the plurality of first pixels, and to generate maturity determination information in accordance with the area size ratio.

Maturity determination device and maturity determination method

A photoelectric conversion device includes: a first optical filter that has a first pattern periodically having a plurality of structures and is formed of a conductive material film disposed on a first photoelectric conversion element with an insulating film therebetween; and a first optical filter that has a second pattern periodically having a plurality of structures and is formed of a conductive material film disposed on a second photoelectric conversion element with the insulating film therebetween. The interval between the first pattern and the second pattern that are adjacent to each other is longer than a period of the structures in the first pattern and a period of the structures in the second pattern.

Photoelectric conversion device

A maturity determination device includes an image capturing device to capture a image including a plurality of first and second pixels; and a signal processing circuit configured to find an area size ratio of an intensity distribution of light of a first wavelength band on the basis of a predetermined reference value based on pixel values obtained from the plurality of first and second pixels, and to generate maturity determination information in accordance with the area size ratio. The first pixel includes a first light transmission filter, and the second pixel includes a second light transmission filter. The intensity of the light of the first wavelength band reflected by the fruits and vegetables varies in accordance with the maturity level, and the intensity of the light of the second wavelength band reflected by the fruits and vegetables is substantially the same regardless of the maturity level.

A photoelectric conversion device capable of preventing anomalous transmission of light of a wavelength that is not supposed to be transmitted and reducing the half-width of a spectral waveform and a method for manufacturing such a photoelectric conversion device are provided. A first photoelectric conversion element is formed on a substrate. A first metal film having a plurality of openings arranged periodically or aperiodically is formed above the first photoelectric conversion element with insulating films interposed therebetween. A second metal film covering a part of the openings in the first metal film is provided.

Photoelectric conversion device and method for manufacturing same

An optical filter configured to transmit light of a predetermined wavelength includes a substrate; a first conductive thin film that is disposed on the substrate and has apertures extending through the first conductive thin film and arranged with a period of less than the predetermined wavelength; and a second conductive thin film at least a portion of which faces the apertures so as to be separated from the apertures.

Optical filter configured to transmit light of a predetermined wavelength

A semiconductor device is provided with the variable resistance element, and a control circuit that controls a resistance state of the variable resistance element by controlling current between a first end and a second end of the variable resistance element. The control circuit causes the variable resistance element to change from a first resistance state to a second resistance state by having a first current flow from the first end to the second end of the variable resistance element. In addition, after a second current smaller than the first current is made to flow from the first end to the second end of the variable resistance element, the control circuit causes the variable resistance element to change from the second resistance state to the first resistance state by having a third current flow from the second end to the first end thereof.

Semiconductor device and control method for semiconductor device

A semiconductor memory device includes a writing circuit and a reading circuit. The writing circuit executes a setting action for converting a resistance of a variable resistance element to a low resistance by applying current from one end side to the other end side of a memory cell via the variable resistance element, and a resetting action for converting the resistance to a high resistance by applying current from the other end side to the one end side via the variable resistance element. The reading circuit executes a first reading action for reading a resistance state of the variable resistance element by applying current from one end side to the other end side of the memory cell via the variable resistance element, and a second reading action for reading the resistance state by applying current from the other end side to the one end side via the variable resistance element.

Semiconductor memory device and semiconductor device

In a semiconductor memory device using a variable resistive element made of a metal oxide for storing information, a voltage amplitude of a writing voltage pulse for changing the variable resistive element to a high resistance state is set within a voltage range in which the resistance value of the high resistance state after the change increases with time. The voltage amplitude is set within the voltage range in which the resistance value of the high resistance state after the change increases toward a predetermined peak with increase in voltage amplitude. When a data error is detected by the ECC circuit, it is estimated that the data that should be in the low resistance state changes to the high resistance state, and the variable resistive elements of all memory cells from which the error is detected are written to the low resistance state to correct the error bit.

Semiconductor memory device

The invention realizes a semiconductor memory device that can efficiently execute a detection of a data error that might possibly occur in a continuous reading action, and a correction of the error data. The semiconductor memory device uses a variable resistive element made of a metal oxide for storing information. During a reading action of coded data with an ECC in the semiconductor memory device, when a data error is detected by an ECC circuit, a writing voltage pulse having a polarity opposite to a polarity of a reading voltage pulse is applied to all memory cells from which the error is detected so as to correct bits from which the error is detected, on an assumption that an erroneous writing has occurred due to the application of the writing voltage pulse having the polarity same as the polarity of the applied reading voltage pulse.

Provided is a semiconductor memory device that is capable of stably programming with desirable controllability to a desired electric resistance state in a random access programming action and is provided with a variable resistance element. Regardless of a resistance state of a variable resistance element of a memory cell that is a target of a writing action (erasing and programming actions), an erasing voltage pulse for bringing the resistance state of the variable resistance element to an erased state having a lowest resistance value is applied. Thereafter, a programming voltage pulse for bringing the resistance state of the variable resistance element to a desired programmed state is applied to the variable resistance element of the programming action target memory cell. By always applying the programming voltage pulse after having applied the erasing voltage pulse, a plurality of programming voltage pulses being sequentially applied can be avoided.

A semiconductor memory device includes a memory cell array in which a plurality of memory cells is aligned in a matrix shape, each memory cell including a two-terminal memory element and a transistor for selection connected in series; a first voltage applying circuit that applies a writing voltage pulse to first bit lines; and a second voltage applying circuit that applies a pre-charge voltage to the first bit lines and second bit lines, wherein in a writing of a memory cell, after the second voltage applying circuit has pre-charged both ends of the memory cell to a same voltage, the first voltage applying circuit applies the writing voltage pulse via the first bit line that is directly connected to the transistor for selection, and the second voltage applying circuit applies the pre-charge voltage to the second bit line directly connected to the memory element.

A semiconductor memory device includes a memory cell array where a plurality of memory cells are arranged in a matrix, each of the memory cells serially connecting a two-terminal type memory element and a transistor for selection, a first voltage applying circuit that applies a write voltage pulse to a bit line, and a second voltage applying circuit that applies a precharge voltage to a bit line and a common line. In writing the memory cell, after the second voltage applying circuit has both terminals of the memory cell previously precharged to the same voltage, the first voltage applying circuit applies the write voltage pulse to one terminal of the writing target memory cell via the bit line, and while the write voltage pulse is applied, the second voltage applying circuit maintains the application of the precharge voltage to the other terminal of the memory cell via the common line.

Semiconductor memory device and method of driving the same

Regardless of a resistance state of a variable resistance element of a memory cell that is a target of a writing action (erasing and programming actions), an erasing voltage pulse for bringing the resistance state of the variable resistance element to an erased state having a lowest resistance value is applied. Thereafter, a programming voltage pulse for bringing the resistance state of the variable resistance element to a desired programmed state is applied to the variable resistance element of the programming action target memory cell. By always applying the programming voltage pulse after having applied the erasing voltage pulse, a plurality of programming voltage pulses being sequentially applied can be avoided. Further, the memory cell array is constituted of even-numbers of subbanks, and the application of the erasing voltage pulse in one subbank and the application of the programming voltage pulse in the other subbank are alternately performed.

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Osaka, Japan

Mitsuru Nakura