Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Hodogaya Chemical Co., Ltd.

Mitsuru Nagata

Tadashi Kojima

Hiroshi Suzuki

Hiromi Kusakabe

Hiroyuki Eguchi

Koichiro Sato

Kazuyuki Wakasugi

Hiroyuki Haga

Toshikazu Oda

Tsunetaka Matsuo

Shin-ichi Majima

Toshitaka Fukunaga

Mariko Terada

A variable resistance device is disclosed, which comprises a first variable resistance circuit and analog switches, a second variable resistance circuit including series-connected first and second resistors, one terminal of the first resistor connected to one terminal of the second resistor and the other terminal connected to one terminal of the first variable resistance circuit, a series-resistor circuit one terminal of which is connected to the other terminal of the second resistor, analog switches connected between the other terminal of the first resistor and nodes of respective resistors of the series-resistor circuit, an analog switch connected between the other terminal of the series-resistor circuit and a node of the first and second resistors, an analog switch connected between a node of the resistors of the series-resistor circuit and the node of the first and second resistors, and a short-circuiting analog switch connected between the first and second variable resistance circuits.

Stepwise zero-data-detection mute circuit

A pair of internal signals are generated by halving a 3-bit 5-valued input signal, neglecting the least significant bit LSB. If the input signal shows the value of an odd number, 1 is added to either of the pair of internal signals to generate first and second signals. &ldquo;1&rdquo; is added to either of the pair of internal signals in an alternating way each time an input signal having the value of an odd number. Signal processing circuits selects a number of output terminals corresponding to the value of the first signal or the second signal out of a plurality of output terminals. All the output terminals are selected with a same probability.

Selecting circuit, digital/analog converter and analog/digital converter

An analog-digital converter capable of outputting stable conversion codes even when an analog signal is input in the vicinity of a boundary between adjacent analog-digital conversion regions. The analog-digital converter as described is provided with ignoring regions between the conversion regions. When the signal level of the analog signal is located within one of the ignoring regions, the analog-digital conversion code outputted from the output circuit is maintained in a next period.

Analog-digital converter analog-digital converting method and volume controller system

A 1-bit D/A converter with a zero detect soft mute function is provided in such a manner that a counter is operated by detecting that a multibit digital signal is all zero for a constant period of time, and a feedback resistor of an op-amp in the analog low-pass filter is decreased stepwise based on a discrete value of the counter so as to be finally short-circuited so that a D/A convert output is fixed at a reference potential. The feedback resistor is composed of a plurality of resistors of first and second groups and first to third analog switches. A first digital control variable resistor is constituted by connecting the resistors of the first group in series and connecting a first analog switch selectively turned on/off in accordance with an output signal other than an LSB of the counter to respective nodes. A second digital control variable resistor is constituted by connecting the resistors of the second group in parallel and connecting a second analog switch controlled by the LSB of the counter to one side resistor in series. The first and second digital control variable resistors are connected in series, and a third analog switch is connected to both ends so as to constitute a feedback resistor.

Variable resistor circuit and a digital-to-analog converter

There is provided an over-sampling D/A converter which has a mute function for fixing an average DC potential of an analog output signal to a predetermined potential, and comprises a .SIGMA. .DELTA. modulator for receiving a multibit digital signal to which a DC offset value is added and then outputting a one-bit non-return-to-zero signal, a signal generator for receiving the non-return-to-zero signal and the clock signal, then generating a return-to-zero signal which is a logical multiplication of the non-return-to-zero signal and the clock signal and a complementary signal of the return-to-zero signal which is a logical addition of the non-return-to-zero signal and an inverted signal of the clock signal, and then adding the return-to-zero signal to the complementary signal of the return-to-zero signal to thus output a polar-return-to-zero signal, and an analog filter for receiving the polar-return-to-zero signal and then outputting an analog signal. Accordingly, because an average DC potential of an output signal at the time of the mute operation-ON is set substantially equal to the average DC potential of the output signal at the time of the mute operation-OFF, variation in the average DC potential in the output signal due to ON/OFF of the mute operation can be prevented. As a result, generation of audible click noises can be prevented.

D/A converter

A reference potential difference canceling circuit is provided in a circuit system of a transmitter side to remove noise caused by impedance Z between circuit systems having different reference potentials from a signal, and to transmit the signal. The reference potential of the circuit system of a receiver side is supplied to an input terminal of the reference potential difference canceling circuit, and its output terminal is connected to an input terminal of an output amplifier to which a transmitting signal is input. A gain of the reference potential difference canceling circuit is set to a reciprocal number of a gain of the output amplifier.

Amplifier for cancelling noise between circuit systems

An amplifier and a semiconductor device according to the present invention are operated at a low voltage and decreased in size and problems such as a noise and an oscillation phenomenon. The amplifier and semiconductor device each includes a first bias generation circuit for generating first and second bias voltages when V1.gtoreq.V2, where V1 is the power supply voltage and V2 is the lower limit of the operation limiting voltage, and for outputting a zero potential when V1&lt;V2, a first amplification circuit for amplifying an input signal by the first bias voltage and for opening an output terminal by the zero potential, a second amplification circuit of a push-pull type operated in response to the input signal and the output signal of the first amplification circuit, and a second bias generation circuit for supplying a bias current to the second amplification circuit by the zero potential when V2&gt;V1.gtoreq.V3, where V3 (&lt;V2) is a lower limit of the operation limiting voltage, and for opening the output terminal when V1.gtoreq.V2. The second amplification circuit performs a push-pull operation when V1.gtoreq.V2 and only one of push-pull transistors performs an amplification operation when V2&gt;V1.gtoreq.V3.

Amplifier and semiconductor device which are operated at a low voltage

A 1-bit D/A conversion circuit according to the present invention comprises an RZ signal generating circuit and a PRZ signal generating circuit. The RZ signal generating circuit receives 1-bit digital data sampled at a predetermined frequency, converts the digital data into a first RZ signal and a second RZ signal complementary to the first RZ signal, shifts the first and second RZ signals with respect to each other by an integral multiple of the predetermined frequency, which is greater than one, and outputs these RZ signals. The PRZ signal generating circuit receives the first and second RZ signals, combines these signals together, and outputs a signal which is a type of a PRZ signal.

1-bit D/A conversion circuit

A counter counts a clock signal. A multiplexer sequentially inputs digital input signals each having a plurality of bits in accordance with an output signal from the counter. A subtracter subtracts a quantized output signal delayed by an n-clock delay element from the input signal. An integrator integrates an output signal from the subtracter. The quantizer quantizes an output from the integrator. The n-clock delay element delays the output signal from the quantizer by n clocks and supplies the delayed signal to the subtracter. A demultiplexer sequentially outputs output signals from the quantizer in accordance with the output signal from the counter. This demultiplexer outputs signals in the input order of the multiplexer.

Digital .SIGMA.-.DELTA. modulator

An identical digital signal and a total of k different DC offset signals are provided to the respective ones of a total of k adders. Each of the adders outputs a signal representing the sum of the digital signal and the DC offset signal. The adders are connected to the respective .SIGMA..DELTA. type D/A converters and the output signals of the k type D/A converters are summed up to form a single output signal. Any two of the levels of the DC offset signals given to the k adders differ from each other by equal to or greater than 0.2% of the full scale value of the .SIGMA..DELTA. type D/A converters. With such an arrangement, the performance of the .SIGMA..DELTA. type D/A converters can be remarkably improved without raising the sampling rate and the number of orders of the type D/A converters.

Sigma delta type digital/analog converter system

A digital sigma-delta modulator comprises an adder, a quantizer, a subtracter, a filter circuit, and a limiter circuit. The adder adds input digital data and feedback data. The quantizer quantizes output data of the adder. The subtracter calculates a difference between output data of the quantizer and that of the adder. The filter circuit digitally processes output data of the subtracter to generate the feedback data. The limiter circuit is arranged in at least one position within an operation loop looping the adder, subtracter, and filter circuit and extracts (n-m)-bit data acquired by eliminating the significant m bit other than MSB from an n-bit data line.

Digital sigma-delta modulator having a limiter circuit

A thermal shutoff circuit for controlling current to an external circuit in response to changes in the temperature of the shutoff circuit. The thermal shutoff circuit includes a source for supplying a voltage which varies with changes in temperature, and a switch circuit responsive to the temperature variable voltage for interrupting the current to the external circuit when the temperature of the shutoff circuit exceeds a predetermined amount. The switch circuit has a detection transistor having a base connected to the temperature variable voltage source for generating a base current responsive to the temperature variable voltage and a compensation transistor connected in series to the detection transistor for generating an equivalent base current.

Thermal shutoff circuit

A data reproduction circuit, which can be used for reproducing audio data from an optical disc, includes a phase-locked loop which has a circuit for detecting polarity inversions of the input signal, a circuit for comparing the phases of a polarity inversion signal with a reference signal, and circuitry for generating an output clock signal which is phase-locked with the input signal, that clock being used to strobe the input signal to remove fluctuation and jitter from the input signal.

Phase locked loop clock recovery circuit for data reproducing apparatus

A differential amplifier circuit having constant mutual conductance characteristics. The circuit comprises first and second differential amplifier units in which each of the emitters of two transistors are connected to a common constant current source via respective diode-junction stacks or resistors. The bases of the individual transistors in the first amplifier unit are connected to different ones of the transistors in the second amplifier unit. On the other hand, the collectors of the individual transistors of the first unit are connected to different ones of the collectors of the second unit, wherein the bases are not connected to each other. Further, the diode-junction stacks or the resistors in the same amplifier unit have the same numbers of diodes or the same resistance, but differ between the amplifier units.

Differential amplifier circuit

3,3-Bis-(4-dimethylaminophenyl)-6-dimethylaminophthalide is produced by oxidizing an alkali metal salt of 2-[4,4'-bis-(dimethylamino)-benzhydryl]-5-dimethylaminobenzoic acid in an aqueous solution of pH of 8 to 14 with hydrogen peroxide, oxygen or air in the presence of a catalyst selected from the group consisting of cobalt compounds and copper compounds.

Growing community of inventors

Naka-gun, Japan

Mitsuru Nagata