Renesas Electronics Corporation

Mitsuru Miyamori

Katsumi Tsuneno

Tetsuya Watanabe

Takashi Shimizu

Risho Koh

According to an embodiment, element models include a first transistor model, a second transistor model, and a variable resistor model. The first transistor model simulates a characteristic of a selection gate transistor whose channel resistance is changed by a selection gate voltage applied to a selection gate. The second transistor model simulates a characteristic of a memory gate transistor whose channel resistance is changed by a memory gate voltage applied to a memory gate. The variable resistor model has a resistance value which is changed in accordance with the selection gate voltage and the memory gate voltage and which is set to correspond to a gap region formed in a lower part of an insulating film insulating between the selection gate and the memory gate. The variable resistor model is provided between the first transistor model and the second transistor model.

Element model and process design kit

The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation.

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Tokyo, Japan

Mitsuru Miyamori