Hitachi, Ltd.

Mitsuru Kawanami

Shinzi Okuhara

Ichiro Ohhinata

Michio Tokunaga

Takuzi Mukaemachi

A semiconductor switch circuit comprises a PNPN switch with a PNPN semiconductor four-layered structure equivalently including first and second transistors and a gate terminal, a load current dividing circuit including at least one transistor, a variable impedance bypass circuit including at least one transistor, and a capacitive element. The base and the collector of the transistor included in the load current dividing circuit are connected to the cathode and the anode of the PNPN switch, respectively. The collector and the emitter of the transistor included in the variable impedance bypass circuit are connected to the P-type base of the second transistor of the PNPN switch and to the emitter of the transistor of the load-current-dividing circuit, respectively. The base of the transistor of the variable impedance bypass circuit is connected to the anode of the PNPN switch through the capacitive element and is controlled for gate turn-off operation. The PNPN switch having self-holding ability is combined with a transistor which does not have self-holding ability but current-amplifying ability to divide the load current into a current flowing through the PNPN switch and a collector current of the transistor. No large load current is imposed on the PNPN switch but most of the load current is passed through the transistors thereby to facilitate gate turn-off operation. Further, the PNPN switch is protected against the rate effect by use of the variable impedance bypass circuit. Thus both large and small load currents can be controlled with a small self-holding current.

Semiconductor switch circuit

A plurality of PNPN switches, each permitting current flow in either, i.e., positive or negative, direction, are arranged at the cross points between the rows and the columns of the speech paths so as to form a matrix. The gate trigger terminal of each PNPN switch is connected with a gating current circuit having a high impedance, which circuit is adapted to control ON and OFF operations of the switch. A plurality of means are provided to selectively turn the gate current circuits on and off so that gate current is supplied continuously for the gate terminal of any desired PNPN switch at least for the time during which the corresponding cross point of the matrix is to be electrically bridged.

Semiconductor channel switch

A semiconductor switch of a PNPN structure comprises a PNPN switch of an equivalently four-layered structure including a P-type anode, N-type cathode, N-type gate and P-type gate, a first NPN transistor, a second PNP transistor, a level shifting circuit, and an impedance element, wherein the impedance element is connected between the collector and emitter of the first transistor, the first transistor has its collector and emitter connected to the P-type gate and N-type cathode respectively, and the second transistor has its emitter and base connected to the P-type anode and N-type gate, respectively, and has its collector connected to the base of the first transistor through the level shifting circuit. In this arrangement, the first transistor is driven by the current flowing through a PN junction at the end on the side of the anode of the PNPN switch and the level shifting circuit, so that the semiconductor switch has a great dv/dt withstanding power, operates with high sensitivity, has a high breakdown voltage in both directions and facilitates the setting of circuit constants.

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Yokohama, Japan

Mitsuru Kawanami