Hitachi, Ltd.

Mitsuru Hirao

Takahide Ikeda

Atsuo Watanabe

Tatsuya Kamei

Kiyoshi Tsukuda

Touji Mukai

Atsushi Hiraishi

Osamu Saito

Katsumi Ogiue

Masanori Odaka

Akira Fukami

Nobuo Tamba

Masayuki Ohayashi

Kouichirou Yamada

Tadashi Kuramoto

Shoji Shukuri

Masataka Minami

Toshiaki Yamanaka

Osamu Saitoo

Ryuichi Saitoo

An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from the surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.

Bimos semiconductor integrated circuit device including high speed

Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.

Method of manufacturing a semiconductor integrated circuit device

Semiconductor integrated circuit device and a method for manufacturing

Method of manufacturing semiconductor integrated circuit device

The structure of a MOSFET and a method for fabricating the same is disclosed, with which it is possible to increase the driving capacity. Heretofore there was a problem that no measures were taken against the decrease in the channel width due to bird's beaks produced at the formation of a field oxide film and that the channel width at the completion of the manufacturing process was smaller than that foreseen during the design of the device. To overcome this problem, a MOSFET is provided in which the junction of the source or the drain is extended up to the end portions in the channel direction so that the effective channel width is determined by the width of the junction on the sides, where the junction is not extended up to the end portions in the channel direction.

Semiconductor device and method for fabricating same

A semiconductor memory device has memory cells each including first and second inverters cross-coupled to each other through first and second interconnecting conductors for forming a bistable circuit and first and second transfer gates connected between the first inverter and address signal conductors and between the second inverter and the address signal conductors, respectively. The first and second interconnecting conductors are arranged substantially point-symmetrically and have at least portions substantially parallel with each other on a surface of a substrate, and IG FETs constituting the first and second inverters have their gate electrodes arranged substantially parallel with one another and extending in a direction substantially perpendicular to the parallel portions of the first and second interconnecting conductors for the cross-coupling on the surface of the substrate.

Semiconductor memory device having memory cells including IG FETs in a

Semiconductor integrated circuit device

An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from a surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.

Herein disclosed is a semiconductor integrated circuit device comprising a SRAM which is composed of a memory cell having its high resistance load element and power source voltage line connected with the information storage node of a flip-flop circuit through a conductive layer. At the same fabrication step as that of forming the plate electrode layer of a capacity element over the conductive layer formed on the portion of the information storage node through a dielectric film, an electric field shielding film for shielding the field effect of a data line is formed over the high resistance load element through an inter-layer insulation film.

Semiconductor circuit device having a plurality of SRAM type memory cell

Growing community of inventors

Ibaraki, Japan

Mitsuru Hirao