Matsushita Electric Industrial Co., Ltd.

Nippon Sheet Glass Company, Limited

Mitsuo Tanaka

Takehiro Hirai

Akihiro Kanda

Masahiro Nakatani

Hideo Yoshizawa

Atsushi Hori

Hiroshi Shimomura

Hideya Esaki

Yoshihiko Horikawa

Yoshiro Fujita

Koichi Nakamura

Yoshimitsu Matsushita

Tetsuya Mizusugi

Kazunori Yuki

Yasuhiko Saikawa

Chie Sugishita

Koichi Tsujiuchi

The present invention aims at providing a method for designing a glass-plate-aimed bending mold making use of a 3-dimensional CAD application for solid models, in a short time with simple operations, by utilizing a previously designed solid model. To this end, there is modified a ring frame of a solid model of a mold stored in an existing-solid-model storing part, such that the ring frame conforms to the shape of a new glass plate, by glass shape replacing means. By using modified parameter reflecting means, the modification of the modifiable parameters inherited from the existing solid-model is reflected to the modified solid model, to thereby optimize the modifiable parameters of a new solid model.

Designing method of a glass-plate-aimed bending mold making use of a 3-dimensional CAD application for solid models

A suction mold has a central suction chamber having a flat shaping surface area and a pair of opposite side suction chambers disposed one on each side of the central suction chamber and having respective curved shaping surface areas. First, a vacuum is developed in the central suction chamber to attract a central area of the sheet of glass against the flat shaping surface area thereof, and then a vacuum is developed in the opposite side suction chambers to attract opposite side areas of the sheet of glass respectively against the curved shaping surface areas.

Method of shaping sheet glass

In a semiconductor apparatus having a PNP bipolar transistor and high voltage resistance, there is formed an oxide insulating layer in the surface region of a P-type semiconductor substrate. In the above semiconductor substrate is formed a P-type collector layer so that at least a part of the P-type collector layer is in contact with said oxide insulating layer. In the surface region of said P-type collector layer is formed a P-type collector contact layer. An N-type base layer is formed in that region on the surface side of said P-type collector layer in which said P-type collector contact layer does not exist. A P-type emitter layer is formed on the surface side of said N-type base layer. A P-type collector-contact/base leakage prevention layer, which has a higher impurity concentration than said P-type collector layer, is formed at least in that region of said P-type collector layer which is in contact with said oxide insulating layer, so as to prevent the generation of a leakage current between said P-type collector contact layer and said N-type base layer.

Method of manufacturing a semiconductor apparatus

A silicon oxide film and a polysilicon film are formed on a silicon substrate and are selectively etched to form a contact hole in a region where an emitter is to be formed. A polysilicon film is laid on the substrate and two polysilicon films are patterned to form an emitter electrode and a gate electrode made of the two polysilicon films which are doped with arsenic. The arsenic is diffused from the polysilicon films of the emitter electrode into the silicon substrate to form an N.sup.+ emitter layer which has a high concentration and is shallow. Consequently, the contamination of a gate insulator film can be prevented from occurring and a bipolar transistor having high performance, for example, a high current amplification factor or the like can be formed.

Semiconductor Bi-MIS device

Method of manufacturing a bipolar transistor

Method of manufacturing Bi-MOS device

A silicon oxide film as a dielectric film and a silicon nitride film or a polysilicon film as a protection film for the silicon oxide film are formed on a silicon substrate. After the two films are selectively etched to form contact holes of a bipolar transistor, a polysilicon film as a conductive film is laid on the entire substrate and selectively etched to form electrodes. In a MIS transistor, the protection film of the silicon nitride film serves as a gate insulator film and the protection film of the polysilicon film serves as a gate electrode. Accordingly, contamination to the gate insulator film at formation of contact holes of the bipolar transistor is prevented, and an excellent semiconductor with Bi-MOS structure is manufactured with low cost.

Semiconductor Bi-MIS device and method of manufacturing the same

The present invention provides a semiconductor device, in particular, a semiconductor device comprising a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same one-conductivity type semiconductor substrate (1) . The IIL comprises an emitter, a base and a collector which are respectively comprised of a high-density n.sup.+ -type first buried layer (5), a p.sup.+ -type second buried layer (8) having a lower impurity density than the n.sup.+ -type first buried layer (5), and at least one of n.sup.+ -type diffused layer (31). The semiconductor device thus constituted makes it possible to increase the emitter injection efficiency while the base impurity density is kept high, and also to decrease the base width, so that the collector-emitter breakdown voltage and current gain of the IIL can be more improved and also the operation speed of the IIL can be made higher.

Semiconductor device including IIL and vertical transistors

In a a semiconductor device having a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same substrate, grooves that reach an n.sup.+ -type buried layer 5 serving as an emitter of the IIL and an n.sup.+ -type buried layer 4 serving as a collector of the vertical npn transistor are formed at the same time, and an oxide film 101 is formed only on the sidewall of each groove; in the grooves, n.sup.+ -type polycrystalline silicon films 103 and 102 are formed, which are made to serve as an emitter lead-out portion of the IIL and a collector wall of the vertical npn transistor, respectively; a p-type diffused layer 17 serving as an injector of the IIL and a p-type diffused layer 18 and p.sup.- -type diffused layer 12 serving as the base thereof are respectively so formed as to be adjoining to the oxide film 101 of the emitter lead-out portion of the IIL; and a p-type diffused layer 16 serving as the base of the vertical npn transistor is so formed as to be adjoining to the oxide film 101 of the collecter wall. The semiconductor device can achieve a smaller cell size, a decrease in parasitic capacitance and an increase in operating speed.

Semiconductor device including integrated injection logic and vertical

A method of fabricating a semiconductor device includes the steps of forming a base diffusion layer in a predetermined region in a semiconductor substrate of a first conduction type, the base diffusion layer being of a second conduction type; forming first insulating films and simultaneously forming an emitter lead-out electrode and a collector lead-out electrode in regions above an emitter-contact-forming region and a collector-contact-forming region, the first insulating films extending on the emitter and collector lead-out electrodes, the emitter and collector lead-out electrodes including impurity corresponding to the first conduction type; forming second insulating films at sides of the emitter and collector lead-out electrodes; forming a base contact; forming a base lead-out electrode including impurity corresponding to the second conduction type; diffusing the impurity from the emitter lead-out electrode, the collector lead-out electrode, and the base lead-out electrode to form an emitter diffusion layer of the first conduction type, a collector contact diffusion layer of the first conduction type; and a base contact diffusion layer of the second conduction type; locating an end of the emitter diffusion layer and a first end of the base contact diffusion layer at positions directly below a portion of the second insulating films which extends at a side of the emitter lead-out electrode; and locating a second end of the base contact diffusion layer and an end of the collector contact diffusion layer at positions directly below a portion of the second insulating films which extends at a side of the collector lead-out electrode.

Method of fabricating semiconductor device

A method of fabricating a semiconductor device includes the steps of forming a base diffusion layer in a predetermined region in a semiconductor substrate of a first conduction type, the base diffusion layer being of a second conduction type; forming first insulating films and simultaneously forming an emitter lead-out electrode and a collector lead-out electrode in regions above an emitter-contact-forming region and a collector-contact-forming region, the first insulating extending films on the emitter and collector lead-out electrodes, the emitter and collector lead-out electrodes including impurity corresponding to the first conduction type; forming second insulating films at sides of the emitter and collector lead-out electrodes; forming a base contact; forming a base lead-out electrode including impurity corresponding to the second conduction type; diffusing the impurity from the emitter lead-out electrode, the collector lead-out electrode, and the base lead-out electrode to form an emitter diffusion layer of the first conduction type, a collector contact diffusion layer of the first conduction type, and a base contact diffusion layer of the second conduction type; locating an end of the emitter diffusion layer and a first end of the base contact diffusion layer at positions directly below a portion of the second insulating films which extends at a side of the emitter lead-out electrode; and locating a second end of the base contact diffusion layer and an end of the collector contact diffusion layer at positions directly below a portion of the second insulating films which extends at a side of the collector lead-out electrode.

The present invention provides a semiconductor device, in particular, a semiconductor device comprising a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same one-conductivity type semiconductor substrate (1). The IIL comprises an emitter, a base and a collector which are respectively comprised of a high-density n.sup.+ -type first buried layer (5), a p.sup.+ -type second buried layer (8) having a lower impurity density than the n.sup.+ -type first buried layer (5), and at least one of n.sup.+ -type diffused layer (31). The semiconductor device thus constituted makes it possible to increase the emitter injection efficiency while the base impurity density is kept high, and also to decrease the base width, so that the collector-emitter breakdown voltage and current gain of the IIL can be more improved and also the operation speed of the IIL can be made higher.

Method of fabricating IIL and vertical complementary bipolar transistors

A glass sheet is heated nearly to its softening point while being passed through a heating furnace. The heated glass sheet is then clamped at its peripheral edge between first and second molds. Thereafter, a third mold is pressed against a central region of the glass sheet with the peripheral edge thereof clamped, thereby to project the central region from one side to the other side thereof. The glass sheet is thus pressed to a desired highly curved shape with no wrinkles or cracks developed therein. The glass sheet is clamped and pressed by a pressing apparatus which includes a fixed concave ring mold as the first mold, and a movable convex mold comprising a peripheral mold assembly as the second mold and a central mold member as the third mold. The glass sheet thus curved is typically used as a front or rear window glass sheet for automobiles.

Method of and system for pressing sheet glass

A sheet glass bending apparatus includes a pressing stage disposed downstream of a heating furnace and a quenching stage disposed downstream of the pressing stage. The sheet glass bending apparatus also comprises a lifting/lowering member for vertically moving a ring mold which supports a lower surface of a glass sheet in the pressing stage, and a shuttle reciprocally movable between the pressing stage and the quenching stage while holding the ring mold, the shuttle being operable to receive the ring mold from and transfer the ring mold to the lifting/lowering member.

Sheet glass bending apparatus

A feeding and processing apparatus has a plurality of intermediate conveyor members disposed between upstream and downstream conveyor means, the intermediate conveyor members being vertically spaced. The feeding and processing apparatus also includes a device for vertically moving the intermediate conveyor members and a device disposed in the vicinity of at least a portion of the intermediate conveyor members for processing objects thereon.

Growing community of inventors

Osaka, Japan

Mitsuo Tanaka