Sony Corporation

Other

Mitsuo Soneda

Takaji Ohtsu

Takashi Noguchi

Toshikazu Maekawa

Takao Tsuchiya

Yoshikazu Hazama

Makoto Kitagawa

Ken Kutaragi

Takahiro Seki

Yuji Hayashi

Akihiko Hashiguchi

Akira Li

Isa Nakamura

Kouji Otsu

Manami Fukuzawa

A semiconductor device includes a memory cell including a thyristor element with a gate having a pnpn structure formed in a semiconductor substrate, and a plurality of access transistors formed on the semiconductor substrate and each connected at a first terminal thereof to a storage node at one terminal of the thyristor element such that a potential at the storage node can be transmitted to bit lines different from each other, the gate of the thyristor element and the gates of the plurality of access transistors of the memory cell being connected to word lines different from one another.

Semiconductor device

A method for forming a Field Effect Transistor (FET) within a strain effect semiconductor layer is disclosed, whereby the source and drain of the FET are formed only in the strain effect silicon layer. The FET may be formed as a gate electrode of a p-channel type field effect transistor, and a gate electrode of a n-channel type field effect transistor on the silicon layer which has the strain effect through a gate insulating film. The sources and drains of p- and n-type diffusion layers are then formed in the silicon layer having the strain effect, on both sides of the gate electrode.

Method of forming N-and P- channel field effect transistors on the same silicon layer having a strain effect

Field effect transistor and fabrication thereof, semiconductor device and fabrication thereof, logic circuit including the semiconductor device, and semiconductor substrate

Method of forming n-and p- channel field effect transistors on the same silicon layer having a strain effect

A voltage controlled delay circuit is formed by m number of gates connected in series, phases of a clock signal and a delay signal are compared by a phase comparator, an up signal or a down signal is output, an integrated signal is generated by an integrator, a voltage signal following this is generated by a buffer and fed back as an operating power source voltage to the voltage controlled delay circuit, and further an internal power source voltage following the voltage signal is generated by a buffer and a pMOS transistor, therefore the internal power source voltage of the required lowest limit can be supplied in response to the frequency of the clock and a reduction of the voltage and conservation of the electric power of the LSI circuit can be achieved.

Voltage generating circuit

An internal power supply circuit, comprising a plurality of charge accumulators, a first power supply terminal, a second power supply terminal, a first switch for connecting the plurality of charge accumulators in parallel to each other in a first state, and a second switch for connecting the plurality of charge accumulators in series with each other in a second state, the charge accumulators connected between the first power supply terminal and the second power supply terminal at either the first state or the second state, and the first state and the second state set repeatedly to raise or lower a voltage between the first power supply terminal and the second power supply terminal.

Internal power supply circuit

A clock distributing apparatus which can decrease the clock skew and can prevent the swing of a signal on clock transmission lines and can achieve a low power consumption, a lower noise of a power supply, and a high speed operation, wherein converts clock signals adjusted in phase to the same phase as a reference clock by a PLL circuit to current signals by voltage/current converters and sends the current signals to clock transmission lines and converts the current signals transmitted to the clock transmission lines to voltage signals by current/voltage converters and sends the voltage signals to circuit blocks of an integrated circuit.

Clock distributing apparatus having V/I and I/V converters

A memory cell circuit which enables reduction of the leak current between a bit line and a memory cell and enables realization of a high speed reading operation and writing operation, wherein a write only circuit and a read only circuit are constructed by a drive transistor and a select transistor, the drive transistor comprising an enhancement type transistor with a threshold voltage set lower than the threshold voltage of the select transistor.

Memory cell circuit independently controlled in writing and reading

A crystal oscillator circuit including a quartz vibrator; an inverter circuit connected in parallel to the quartz vibrator and comprised of at least two transistors connected at their output ends to a first power-supply potential or a second power-supply potential lower than the first power-supply potential; a first current mirror circuit, with one current input-output end connected to a connection line with the inverter circuit of the first power-supply potential, the other current input-output end connected to the output end of the oscillator circuit; and either a second current mirror circuit having two current input-output ends, one current input-output end connected to a connection line with the inverter circuit of the second power-supply potential, the other current input-output end connected to the output end of the oscillator circuit, current flowing to one current input-output end, current flowing to the other current input-output end, and the level of the output end of the oscillator circuit being shifted to the level of the second power-supply potential when the output end of the inverter circuit is connected to the second power-supply potential or a circuit for shifting the level of the output end of the inverter circuit to the level of a second power-supply potential in accordance with the level of the input end of the inverter circuit when the output end of the circuit is connected to a second power-supply potential.

Crystal oscillator circuit

A level shifting circuit for converting a lower logic level into a higher logic level is arranged to prevent a large through current from flowing when the level of an input signal varies. A latch circuit for latching an input binary signal comprises first and second transistors to which there are connected in series third and fourth transistors, respectively, for blocking a current during the level shifting period. Fifth and sixth transistors having a small current capacity are connected parallel to the set of first and third transistors and the set of second and fourth transistors, respectively, to quickly respond to a level change. The fifth and sixth transistors may be dispensed with.

Level shifting circuit

An apparatus for sensing an electric charge appearing on at least one bit line of a memory cell comprises a pair of P-channel MOS (Metal Oxide Semiconductor) transistors whose sources are commonly connected, a pair of N-channel MOS (Metal Oxide Semiconductor) transistors whose sources are commonly connected, both pairs of the PMOS and NMOS transistors carrying out latch operations according to control signals supplied to their sources to sense the electric charge appearing on either a first or second bit line. In at least one of the pairs of PMOS and NMOS transistors, the gate of each MOS transistor is connected to either the first or second bit line via a capacitor, a first switching element is disposed between the drain of each MOS transistor and gate thereof, and a second switching element is disposed between the drain of each MOS transistor and a junction to either the first or second bit line. When control voltages applied to both sources of the PMOS transistors and NMOS transistors are changed and the switching elements are switched over during a precharge interval and sensing operation interval, the capacitors store voltages according to the respective threshold voltages of the PMOS and NMOS transistors so that divergence in the threshold voltages can be compensated for.

Bit line charge sensing apparatus having CMOS threshold voltage

Memory cell circuit has a pair of transistors in which the gates are connected to the drains, a first and a second access transistor whose gates are connected to a read line and which are located between gate-drain connection of said pair of transistors and a pair of bit lines. The memory cell circuit also includes a third access transistor whose gate is connected to the read line and is located in the circuit between said first access transistor and the gate of said pair of transistors corresponding to the first access transistor, and a fourth access transistor whose gate is connected to the read line and is located in the circuit between said second access transistor and the gate of said pair of transistors corresponding to the second access transistor.

Memory cell circuit

Liquid crystal display apparatus

A sense amplifier includes two cross-coupled field effect transistors capacitively coupled to respective bit lines from a memory cell. During a precharging operation two capacitors are charged to precharged voltages indicative of the threshold dispersion voltage between the two transistors. Thereafter, during a sensing operation, the precharged voltages are applied to the gates of the transistors to compensate for the threshold dispersion voltage.

Growing community of inventors

Kanagawa, Japan

Mitsuo Soneda