Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Nec Corporation

Mitsuo Saito

Takeshi Aikawa

Kenji Minagawa

Toshio Okamoto

Tsukasa Matoba

Ken-ichi Maeda

Shigehiro Asano

Seiji Maeda

Yasuhiko Kurosawa

Akio Mori

Hideo Segawa

Hiroo Hayashi

Shigeaki Iwasa

Mitsuyoshi Okamura

Miwako Doi

Kenichi Maeda

Toru Imai

Kenta Yasufuku

Hiroshi Nozue

Junji Mori

Shin Sungho

Kenichi Mori

Yukihito Oowaki

Shinichiro Shiratake

Ryo Fukuda

Yuzo Shimada

Takehiro Hasegawa

Kenji Takeda

Shigeyoshi Watanabe

Hirokazu Tohya

Ichiro Tomoda

Osamu Myohga

Nobuyuki Ikumi

Shiro Yoshida

Masako Yoshida

Masahide Ohhashi

Ryo Maniwa

Yoichi Sadamoto

Ikiko Nishida

Nobuhiro Yoshida

Osamu Wakamori

An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.

Virtual address cache memory, processor and multiprocessor

An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain cache data with the effective page tag or a page offset as a cache index; and a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the cache index.

Effective address cache memory, processor and effective address caching method

A multiprocessor system including a master processor, a plurality of processor elements, each of which is provided with a local memory, the processor elements being controlled in accordance with commands from the foregoing master processor, and a global memory shared by the plurality of processor elements is disclosed. The processor elements are provided with a command pooling buffer capable of accumulating a plurality of commands, respectively. DMA controllers are also provided with a command pooling buffer capable of accumulating a plurality of commands, respectively. The master processor persistently issues a plurality of commands to the DMA controller and each processor element. A counter array manages the number of the issued commands which have received no response. When the responses are returned with respect to all issued commands, the counter array notifies the master processor of this.

Multiprocessor system and control method thereof

A laminate printed circuit board loaded with transistors, ICs (Integrated Circuits) or LSIs (Large Scale Integrated Circuits) and a method of producing the same are disclosed. The circuit board includes a signal layer, a ground layer and a power supply layer sequentially laminated with the intermediary of insulation layers. An impedance adding circuit is formed in the power supply layer. A magnetic layer is positioned at least above or at least blow the impedance adding circuit. The circuit board with this configuration reduces power supply noise to a noticeable degree.

Laminate printed circuit board with a magnetic layer

A memory management and protection system for realizing a high speed execution and a proper and flexible memory access control for multiple programs sharing an identical logical address space. In the system, the memory access is permitted according to a segment identifier identifying a segment in the logical address space, and a memory protection information for a region in each segment including a target right permission to indicate assigned rights to make a memory access from the region to each of the segments, and an execution permission to indicate a type of the memory access permitted by the right permission. Alternatively, a memory access can be permitted by using an access control list to be attached to each address table entry, which stores a plurality of program numbers identifying programs which are permitted to make accesses to the logical address stored in each address table entry, among which one that matches with the current program number is to be searched. Also, it is preferable to allocate a plurality of programs within a limit of available memory protection capacity to an identical logical address space, without any overlap between adjacently allocated address regions.

Memory management and protection system for virtual memory in computer

A method for managing virtual address space in which programs designed for smaller virtual address spaces in the multiple virtual memory scheme can be collectively allocated to a single enlarged virtual address space in the single virtual memory scheme efficiently, without requiring any change in the programs themselves, such that the entire virtual address space becomes available in the compatible mode. In the method, the effective addresses to be used during an execution of a program designed for a smaller address space are calculated by combining an appropriate address base for this program specifying upper bits of the effective address and lower bits of the virtual addresses for a region of the enlarged address space to which this program is allocated. The address base may be replaced by the upper bits of the starting address of the program in the enlarged address space which are retained throughout the effective address calculation. The method may use a compatible mode address region to be used in executing a program designed for a smaller address space which has virtual addresses identical to those to which this program is designed to be allocated in the smaller address space.

Method for managing virtual address space at improved space utilization

In a semiconductor memory device wherein a plurality of memory cell units formed by connecting a plurality of memory cells in series are provided and each of the memory cell units is connected to a bit line, the semiconductor memory device comprises control circuit for directly reading data of a register cell during a reading operation when the previous row address designates the same memory cell as the present row address, and a data changing controlling circuit for changing data of an arbitrary memory cell of the memory cell unit to data of the memory cell closest to the bit line contact in the memory cell unit, and a row decoder for corresponding row addresses which select the memory of memory cell units, to the upper addresses than the parts of the row addresses which select a memory unit among the memory cell units.

Semiconductor memory device

A cache memory system capable of realizing a high level performance and a high speed processing with a simple control. The system may use a plurality of processing units and a plurality of corresponding cache memory units, where all the cache tag memory units of the cache memory units are collectively arranged in relation to the primary processing unit which carries out a memory access address calculation. The system may also use a refilling control such that a new refilling operation for a newly occurred cache miss in the primary cache memory unit is started in parallel to another refilling operation for a previously occurred cache miss in the primary cache memory unit before that another refilling operation is completed. The system may also use a refilling control such that the refilling operation is started by making an access to the secondary memory unit with a starting address at which the cache miss occurred in the primary cache memory unit, and continued by making subsequent accesses to the secondary memory unit with addresses obtained by adding an increment to the starting address one by one.

Cache memory system for multiple processors with collectively arranged

An electronic computer which uses different bus protocols to transfer information for processor-to-processor communication and for processor-to-peripheral communication. The electronic computer includes an address buffer translator which translates a virtual address to a physical address and produces a bus protocol specifying signal. A bus interface changes bus protocols in accordance with the bus protocol specifying signal in order to permit a transfer of a physical address and data on the bus. In another embodiment, when the data in a cache memory is changed, a dirty bit for the cache memory is set but a corresponding dirty bit in the address translation buffer is not changed until a copy-back operation from the cache memory to a main memory occurs. The dirty page bit of the address translation buffer is changed utilizing software.

Computer system which switches bus protocols and controls the writing of

A parallel processing type processor system with trap and stall control functions capable of operating without increasing the cycle time, such that the lowering of the clock frequency in the system can be prevented. In the system, the processor units are controlled such that when an exception is caused in an execution of at least one of the instructions supplied to the processor units concurrently, the processings of all of the instructions supplied to the processor units concurrently are aborted. In addition, the processings of the instructions supplied to the processor units concurrently are stalled when it is not possible to deny a possibility for an occurrence of an exception in the execution of the instructions supplied to the processor units concurrently.

Parallel processing type processor system with trap and stall control

The branch prediction device of this invention is for use in a pipeline processor where a plurality of instructions are simultaneously processed in various stages, such as the fetch stage, execution stage, memory access stage and register write stage. A two-port branch prediction buffer enables simultaneous operation of the registration and retrieval processes so that a previously registered address can be obtained during the same clock pulse as registration of another branch address occurs.

Branch prediction device enabling simultaneous access to a

On the basis of, e.g., input items, attribute values, and titles, their categories are analyzed by using a proper noun dictionary, a concept dictionary, and a numeric attribute name dictionary. On the basis of the analyzed categories, changes in attribute values are analyzed in accordance with inference rules, and a keyword for describing a background state of presentation is extracted. A background material suitable for presentation is selected from background materials such as images and sounds in accordance with the extracted keyword. The selected background material is displayed in combination with a graph which is formed in accordance with content data about an object to be presented.

Presentation support system

An electronic computer according to this invention is capable of executing a plurality of instructions simultaneously. It is characterized by comprising a flag adding section for judging whether or not each of a plurality of instruction is either a delayed branch instruction or a squash branch instruction, and based on the results, adding a flag indicating an abort condition to each instruction, and a command execute abort section for aborting execution of each instruction on the basis of whether or not the flag added to each instruction to indicate the abort condition and each branch instruction hold true.

Electronic computer which executes squash branching

Growing community of inventors

Yokosuka, Japan

Mitsuo Saito