Renesas Electronics Corporation

Other

Mitsuo Nissa

Satoshi Kura

Keiji Sakamoto

Taichi Iwasaki

Toru Kawasaki

Naotaka Kamishita

A first transistor required for decreasing leak current and a second transistor required for compatibility of high speed operation and low power consumption can be formed over an identical substrate and sufficient performance can be provided to the two types of the transistors respectively. Decrease in the leak current is required for the first transistor. Less power consumption and high speed operation are required for the second transistor. The upper surface of a portion of a substrate in which the second diffusion layer is formed is lower than the upper surface of a portion of the substrate where the first diffusion layer is formed.

Method of manufacturing a semiconductor device with an upper surface of a substrate at different levels

Semiconductor device with an upper surface of a substrate at different levels and method of manufacturing the same

A first transistor includes a first gate insulating film, a first gate electrode, and a first sidewall. A second transistor includes a second gate insulating film, a second gate electrode, and a second sidewall. A capacitive element is connected to one side of source and drain regions of the second transistor. The first gate insulating film has the same thickness as that of the second gate insulating film, and the first gate electrode has the same thickness of that of the second gate electrode. The width of the second sidewall is larger than the width of the first sidewall.

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device is disclosed that can include a gate electrode ( ) having a lower layer ( ) and a higher layer ( ), a mask insulating film ( ) formed over a higher layer ( ). A side surface insulating film ( ) may be formed on sides of a gate electrode ( ) and a side wall insulating film ( ) may be formed on the sides of a gate electrode ( ) and mask insulating film ( ). A low density impurity region ( ) may be formed with a gate electrode ( ) and side surface insulating film ( ) as a mask. A higher density impurity region ( ) may be formed with a gate electrode ( ) and side wall insulating film ( ) as a mask. A contact plug ( ) may be formed between side wall insulating films ( ) that contacts a higher density impurity region ( ). A gate electrode ( ) may have a reverse tapered shape when viewed in cross section. A lower layer ( ) may have a reverse tapered shape and/or a side surface insulating film ( ) may have a greater thickness on sides of a higher layer ( ) than on a lower layer ( ).

Semiconductor device and its manufacturing method

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Tokyo, Japan

Mitsuo Nissa