Nec Corporation

Fujitsu Corporation

Nippon Telegraph and Telephone Public Corporation

Nippon Telegraph and Telephone Corporation

Nippon Electric Co., Ltd.

Kokusai Denshin Denwa Co., Ltd.

Mitsuo Nishiwaki

Naoki Mukawa

Hideo Kuroda

Shuzo Tsugane

Kiichi Matsuda

Makoto Hiraoka

Yoshinori Hatori

Toru Shibuya

Tooru Yasuda

Tooru Amano

Sakae Okubo

Syuzo Tsugane

For decoding by the use of a decoder buffer memory an encoded video signal into which an encoder input signal is encoded with data compression on a basis of frames, a decoding device comprises a control signal producing unit for delivering a decoder control signal to a decoder when the frame of data written into the buffer memory coincides with the frame of data read out of the buffer memory. Responsive to the control signal, the decoder produces a supply control signal to the buffer memory to stop delivery of the read-out data to the decoder. Preferably, the decoding device should comprise a processing unit for producing frame pulses at heads of the respective frames of the encoded video signal. A counter counts the frame head pulses to make the write-in data and the read-out data indicate frame numbers for use in the signal producing unit. Alternatively, the decoding device may receive an encoded video signal in which frame number data are included for use in the signal producing unit.

Decoding device capable of producing a decoded video signal with a

An inter-frame encoding/decoding equipment for television signals consists of inter-frame encoding equipment encoding a difference between television signals and the output of a frame memory and inter-frame decoding equipment which receives an encoded signal sent from the inter-frame encoding device via a transmission line, which decodes by adding the output of the frame memory to the encoded signal. The inter-frame encoding equipment is provided with a first operation circuit which operates the remainders obtained by dividing, by a predetermined value, the number of bits of logic '1' in the bit groups into which the output or the input of the frame memory is divided by a predetermined unit. The inter-frame decoding equipment is provided with a second operation circuit which operates the remainders obtained by dividing, by a predetermined value, the number of bits of logic '1' in the bit groups into which the output or the input of the frame memory is divided by a predetermined unit. The inter-frame decoding equipment is further provided with a comparator circuit which compares and checks the values operated by the first and the second operation circuits to detect a transmission error.

System for detecting a transmission error

A video signal frame memory is refreshed without requiring either a separate transmission line or the transmission of bursts of data. This is done by dividing the frame signals into blocks of data, which are further divided into lines and sub-blocks. During each frame, refreshing signals are sent on a sub-block basis, thereby distributing the refreshing control signals and preventing many signals from being sent in bursts.

Method and arrangement for refreshing a frame memory in an interframe

In a multiplexing system wherein data from a plurality of terminal units are multiplexed in time slots shared to the terminal units and coded picture data are multiplexed at least in time slots shared for picture, there are provided picture signal encoding means operating at a clock frequency independent of a clock frequency for a transmission path, a buffer memory circuit for storing the coded picture data outputted from the picture signal encoding means, a data detecting circuit for detecting presence or absence of output data from the plurality of terminal units and a multiplexing circuit which shares coded picture data read out from the buffer memory circuit to a time slot or time slots of terminal units whose output data are not detected by the data detecting circuit and which shares, to time slots of terminal unit whose output data are detected by the data detecting circuit, output data of these terminal units, thereby adaptively sharing coded picture data to the time slots for the terminal units.

Multiplexing system

In a digital data communication network comprising digital data transmitting and receiving devices (111, 122) and first and second digital communication paths (16, 17) connected to each other and to the transmitting and the receiving devices, respectively, a stuffing circuit (23) is controlled by a control signal producing circuit (24) so as to stuff and not to stuff an input bit sequence when at least one of the first and the second digital communication paths has a restricted transmission characteristic and when both of the communication paths have an unrestricted transmission characteristic. Preferably, necessity and unnecessity of stuffing should be detected for a leading and a trailing part of each block with a shorter interval of time than for other parts of the block. More preferably, some of binary one bits placed at the beginnings of the respective blocks are used as a part of a multiframe synchronization pattern for a signal transmitted through the communication paths.

Digital data transmitting device for communication paths of restricted

A system for coding video signals e.g. television signals in block units is disclosed. The coding system comprises a synchronization detector for detecting a frame synchronization from the video signal, and a block former operative to divide the video signal in block units per a predetermined number of lines by using a picture frame synchronization signal detected by the synchronization detector as a reference. When the number of lines included in a block immediately before the subsequent picture frame synchronization signal is less than the predetermined number of lines, the block former designates the block as an ineffective block. The coding system further comprises a coder operative to apply a coding processing to the blocks except for the ineffective block designated by the block former in accordnace with a predetermined coding procedure, and transmitter operative to multiplex coded data outputted from the block former and coder, position information of the first block immediately after the picture frame synchronization signal, and the number of lines within the ineffective block so as to transmit the multiplexed signal thus obtained. Thus, when the input video signal is asynchronously switched, the coding system necessarily executes only a processing per each block, thus providing a reproduced picture image free from distortion on the side of a receiving station.

System for coding video signal in block unit

Inter-frame encoding/decoding equipment for television signals includes inter-frame encoding equipment generating an encoded signal by encoding a difference between television signals and the output of a frame memory and inter-frame decoding equipment which receives the encoded signal sent from the inter-frame encoding device via a transmission line. The decoding equipment decodes by adding its output of the frame memory to the encoded signal. The inter-frame encoding equipment is provided with a first operation circuit which calculates remainders obtained by dividing a predetermined value, into bit groups of the output or the input of the frame memory. The inter-frame decoding equipment is provided with a second operation circuit which calculates remainders obtained by dividing, the predetermined value, into the bit groups of the output or the input of its frame memory. The inter-frame decoding equipment is further provided with a comparator circuit which compares and checks the remainders calculated by the first and the second operation circuits to detect a transmission error.

A digital data transmission system comprises a transmitter and a receiver, said transmitter comprising storage means for temporarily storing a data bit string forming a coded digital video signal, means for supplying a read request signal for reading out said data bit string from said storage means, means for forming one frame out of time slots alloted to a frame synchronization bit, a predetermined number of data bit of said data bit string and a dummy flag bit which indicates whether or not a dummy bit exists in said one frame, means for detecting whether or not a fixed bit pattern is formed in said one frame, means for providing said dummy bit to a predetermined one of said time slots in response to the result of said detection, means for inserting a dummy flag bit indicative of whether or not the dummy bit has been inserted to a time slot for said dummy flag bit, means for supplying a data bit which have dropped out by addition of said dummy bit to said frame forming means so that said dropped data bit is inserted as a part of said data bits forming a succeeding frame, and means for suspending the supply of said read request signal for the bit corresponding to said dropped data bit; said receiver comprising an input terminal for receiving in serial fashion the transmitted data bit string supplied from said transmitter, means for detecting said dummy flag bit in said transmitted data bit string, and means for separating said transmitted data bit string into a dummy bit and input data bits in response to the detection of said dummy flag bit.

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Tokyo, Japan

Mitsuo Nishiwaki