Sharp Kabushiki Kaisha Corporation

Mitsuo Morihisa

Hideyuki Akao

Takehiko Sasaki

Hidetoshi Maeda

Norio Muguruma

Tadao Inoue

An interface circuit is disposed between an NMOS random access memory and a PMOS central processor unit in order to ensure accurate data transfer therebetween. The interface circuit includes a pull-up system for pulling up a signal transmission line to a desired voltage level. The pull-up system is energized when the data signal is transferred from the NMOS random access memory into the PMOS central processor unit. The pull-up operation is not conducted when the data signal is transferred from the PMOS central processor unit into the NMOS random access memory.

Voltage level compensating interface circuit for inter-logic circuit

A memory protection system includes an auxiliary power supply source for maintaining information stored in a random access memory when the main power supply is terminated. When the main power supply voltage level becomes lower than a preselected level, a detection unit develops a control signal for applying a disabling signal to a chip selection terminal included in the random access memory, whereby a load such as a central processor unit connected to the random access memory is electrically disconnected from the random access memory to minimize the power dissipation.

Memory protection system

A power supply circuit includes a rectifier for converting an alternating voltage to a DC voltage for driving a single chip LSI microcomputer control system in, for example, a microwave oven. A switching circuit is included in the power supply circuit for developing an output DC voltage only after the DC voltage derived from the rectifier reaches a preselected level. The switching circuit includes large current transistors connected in the Darlington fashion, whereby the power supply circuit develops the output DC voltage with a short leading transient period which is required for developing an auto-clear signal in the single chip LSI microcomputer control system.

Power supply/auto-clear circuit

In a crystal oscillator for solid state wristwatches, the input of an impedance converter is connected to the output of a complementarily connected transistor amplifier which performs linear operation within its essential operating range, to thereby stabilize and decrease the output impedance of the amplifier on the average. The impedance converter includes one or more active elements such as MOSFET's, junction type FET's and bipolar transistors. A quartz resonator is connected between the input of the complementarily connected transistor amplifier and the output of the impedance converter.

Crystal oscillator implemented with CMOS technology

Zero adjustment of second information in an electronic timepiece is carried out upon receiving a command from the operator. 'Increment one' is performed upon minute information when the second information is between 24 and 59 seconds when the zero adjustment command is generated. Minute information is not changed when the second information is between 0 and 23 seconds when the zero adjustment command is generated.

Zero adjustment in an electronic timepiece

In a crystal oscillator for solid state wristwatches, the input of an impedance converter is connected to the output of a complementarily connected transistor amplifier which performs linear operation within its essential operating range, thereby stabilizing and decreasing output impedance of the amplifier on the average. The impedance converter includes one or more active elements such as MOSFET's, junction type FET's and bipolar transistors. A quartz oscillator is connected between the input of the complementarily connected transistor amplifier and the output of the output impedance converter.

Growing community of inventors

Nara, Japan

Mitsuo Morihisa