Fujitsu Corporation

Nippon Telegraph and Telephone Public Corporation

Mitsuo Kakuishi

Yutaka Awata

Nobukazu Koizumi

Takanori Iwamatsu

Norio Ueno

Seiji Kato

Yasuo Ohtomo

Tsuyoshi Ueshima

Seiji Miyoshi

Norio Murakami

Kaoru Chujo

Hiroyuki Kiyanagi

Atsushi Iwata

Akihiko Ito

Hirokazu Fukui

Atsushi Manabe

Hiroaki Itokawa

Seiji Mikyoshi

Yuko Kurosaki

A digital modulator and digital demodulator with quadrature amplitude modulation (QAM) schemes, which are designed to modulate or demodulate RZ-coded baseband signals. The digital modulator comprises first to fourth roll-off filters and a first and second inverters connected to the second and fourth roll-off filters. It also comprises a parallel-to-serial converter to successively selects the outputs of the first roll-off filter, third roll-off filter, first inverter, and second inverter. A D/A converter converts the selected digital signal stream into an analog signal. The roll-off filters and inverters operate at a predetermined clock frequency, while the parallel-to-serial converter and the D/A converter work at a frequency four times the predetermined clock frequency. The digital demodulator reverses the above modulation process to reproduce the baseband signals.

Digital modulator and digital demodulator

A clock phase detecting circuit is provided which is arranged in a receiving section of a multiplex radio apparatus. Difference detecting unit detects the difference between input and output signals to and from an equalizing circuit, and squaring unit squares the detected difference. The squared value thus obtained shows a minimum value when the phase of a clock signal output from a clock regenerating circuit coincides with a normal position of signal point. Therefore, phase adjusting unit outputs a control signal to the clock regenerating circuit while monitoring the squared value, to adjust the phase of the clock signal output from the clock regenerating circuit so that the squared value output from the squaring unit may be minimized.

Clock phase detecting circuit

A digital modulator and digital demodulator with quadrature amplitude modulation (QAM) schemes, which are designed to modulate or demodulate RZ-coded baseband signals. The digital modulator includes first to fourth roll-off filters and a first and second inverters connected to the second and fourth roll-off filters. It also includes a parallel-to-serial converter to successively select the outputs of the first roll-off filter, third roll-off filter, first inverter, and second inverter. A D/A converter converts the selected digital signal stream into an analog signal. The roll-off filters and inverters operate at a predetermined clock frequency, while the parallel-to-serial converter and the D/A converter work at a frequency four times the predetermined clock frequency. The digital demodulator reverses the above modulation process to reproduce the baseband signals.

Digital quadrature amplitude modulators

An echo canceller is disclosed which generates an echo replica based on a transmit signal to cancel an echo. The echo canceller includes a linear echo canceller circuit for generating an echo replica of the transmit signal in the absence of distortion. The echo canceller further includes a waveform-distortion compensation circuit, coupled with the linear echo canceller circuit, for generating an echo replica for compensating waveform distortion occurred in an echo response when the transmit signal is distorted. In the echo canceller, the echo is canceled by use of the echo replica generated in the linear echo canceller circuit in the absence of distortion in the transmit signal, and is canceled by use of the echo replica generated in the waveform-distortion compensation circuit when the transmit signal is distorted.

Echo canceller and waveform-distortion compensation device

A data receiving device for reproducing a received symbol from a received data signal, includes a timing recovery circuit for controlling a phase of sampling the received data signal, by using pre-cursor information, the timing recovery circuit produces sampling phase control information by eliminating a high frequency component for the pre-cursor information, accumulating eliminated output, comparing accumulated output with a positive or a negative threshold value and subtracting the threshold value from compared output. The data receiving device further includes a masking circuit for masking the sampling phase control information when no-signal data or frame is detected in the received data signal.

Data receiving device for reproducing a received symbol from a received

A digital subscriber loop interface unit, connected to a digital subscriber loop, includes an echo canceler for carrying out a echo canceling operation, a decision feedback equalizer for carrying out an equalizing operation, and a transversal filter, provided in at least one of the echo canceler and the decision feedback equalizer, in which a plurality of taps among all taps are grouped into groups, each group including a predetermined number of taps continuously arranged, a single tap coefficient being assigned to the taps in each group. A digital subscriber loop interface unit may include an echo canceler for carrying out a echo canceling operation by using a value obtained by adding +1 to a symbol value represented by a 2B1Q code. Further, the echo canceler may have a jitter echo canceler in which a convolution operation is carried out by using a value obtained by adding +1 to a symbol value represented by the 2B1Q code, the tap coefficient used in the convolution operation is changed in accordance with a time elapsing from occurrence of the jitter. Furthermore, a digital subscriber loop interface unit may have a low-pass filter in which a filter coefficient is changed based on whether the decision feedback equalizer is in or after a pull-in step.

Digital subscriber loop interface unit

The present invention provides, a two-system A/D converter, which provides a digital output signal with a higher conversion precision than is achieved by a single-system A/D converter. Conversely, by using a two-system D/A converter with a lower conversion precision, the present invention provides an analog output signal with a higher conversion precision than is achieved by a single-system D/A converter. Further, a digital signal clock changing unit produces data by performing high sampling of the first digital data trains, and the second digital data is synchronized with a second clock through an interpolation processing based on the timing difference between the first and second clocks. A high-precision A/D and D/A converter apparatus is thus realized by using two pulse code modulation coder/decoders (PCM.CODECs) and one digital signal processor (DSP) in a small, inexpensive structure.

Signal processing system for use in a digital signal clock changing

The present invention provides a two-system A/D converter, which provides a digital output signal with a higher conversion precision than is achieved by a single-system A/D converter. Conversely, by using a two-system D/A converter with a lower conversion precision, the present invention provides an analog output signal with a higher conversion precision than is achieved by a single-system D/A converter. Further, a digital signal clock changing unit produces data by performing high sampling of the first digital data trains, and the second digital data is synchronized with a second clock through an interpolation processing based on the timing difference between the first and second clocks. A high-precision A/D and D/A converter apparatus is thus realized by using two pulse code modulation coder/decoders (PCM.CODECs) and one digital signal processor (DSP).

Signal processing apparatus

A digital adaptive equalizer equalizes received signals through digital filtering operations by changing filtering coefficients. It comprises a coefficient calculating unit for calculating the filtering coefficients by using one kind of parameters, such as distance, as an input to a function corresponding to the filtering coefficients and a filtering operation executing unit for executing digital filtering operations based on the filtering coefficients. A variable lag filter for adjusting the phase delay of received received signals is provided. A coefficient converting unit calculates a part or all of tap coefficients of the filter using at least one piece of timing control information.

Received data adjusting device

Circuit for detecting object signal from input signal

A digital loop filter includes a first loop filter for generating first phase control information at variable time intervals on the basis of phase error information indicating a phase difference between a first signal and a second signal. A second loop filter detects a frequency deviation between the first and second signals from the phase error information and generates second phase control information with a period inversely proportional to the frequency deviation. An adder generates finalized phase control information obtained by adding the first phase control information and the second phase control information to each other.

Digital loop filter and digital PLL circuit using the same

The invention provides a digital PLL circuit wherein the integration time constant of a random walk filter can be varied adaptively in response to a frequency error. A master clock signal having a frequency equal to N (integral number) times that of an input clock signal is normally divided by N by a divider, and the division output of the divider and the input clock signal are compared in phase with each other by a phase comparator. The dividing ratio of the divider is temporarily varied in accordance with a result of the comparison so as to make the phases of the division output and the input clock signal coincide with each other to establish synchronism between them. A variable step number random walk filter is interposed between the phase comparator and the divider and has a selectively settable integration time constant, and an integration time constant setting circuit varies the step number of the random walk filter in accordance with information of a last phase controlling direction or directions and information of a phase controlling direction at present to vary the integration time constant of the random walk filter.

Digital PLL circuit

An impulse response of a litter may change in the output of a filter unit immediately after the generation of a litter according to a sampling timing signal from a timing regenerating unit if a filter unit is provided between an A/D converting unit and an echo canceler. In this case, a selecting unit in a jitter compensating unit compensates an uncanceled echo through each of the outputs sequentially selected by a plurality of adaptive filter unit. Plural sets of tap coefficients are stored in a tap coefficient storage unit, from which the selecting unit sequentially reads them to operate one adaptive filter unit, thereby reducing the size of a jitter compensating circuit.

Jitter compensating device

A transversal filter has a transfer function for which a zero point occurs outside a unit circle on z plane and thus the output waveform has a ringing characteristic having a change from negative to positive around a precursor and before a main cursor and is associated and integrated with another transversal filter, thereby forming a waveform shaping decimation filter or a pulse shaping high-pass filter. The waveform decimation filter can eliminate a high frequency noise, changes a high frequency input data to a low frequency output data, and performs a waveform shaping operation. Therefore it cannot require a pulse shaping filter separated from the decimation filter. The pulse shaping high-pass filter includes a pulse shaping filter whose number of the taps is decreased and performs high-pass filter function. A pulse shaping filter whose number of the taps is decreased can be used separately from the high-pass filter.

Growing community of inventors

Kawasaki, Japan

Mitsuo Kakuishi