Fujitsu Corporation

Fujitsu Vlsi Limited

Mitsuo Higuchi

Kiyoshi Miyasaka

Atsushi Takeuchi

Hideki Arakawa

Masanobu Yoshida

Kiyonori Ogura

Takao Akaogi

Kohji Shimbayashi

Kohichi Maeda

Manabu Tsuchida

Kazuhisa Nakamura

Yasuhiro Nakaoka

Ryoji Hagihara

An electrically erasable and programmable read-only semiconductor memory includes a cell array portion formed by arranging in matrix a plurality of memory cell portions each having a cell transistor, a unit for selecting a cell transistor of the cell array portion, and a read circuit for generating a plurality of data, for each of a plurality of reference current values, for indicating whether or not a current value of a current flowing through a cell transistor selected and brought into a read state is greater than a plurality of reference current values inclusive of reference current values of the case where judgement is made as to whether the cell transistor brought into the read state is under the state where the cell transistor should be regarded as storing a first logical value, or under the state where the cell transistor should be regarded as storing a second logical value. This construction can detect in advance a cell transistor having the possibility of the loss of information, and acquires the chance for rewrite or the exchange of the cell transistor used. Accordingly, the loss of the information can be prevented and system reliability can be improved.

Semiconductor memory device with function of preventing loss of

An electrically erasable and programmable memory device includes a memory cell array including a plurality of blocks, each including electrically erasable and programmable memory cells. A data input/output unit transfers data between the memory cell array and an external device. An address conversion unit converts an external address signal into a decoded signal applied to the memory cell array so that the correspondence between the external address and the plurality of blocks is changed so as to equally access the plurality of blocks for programming. The number of the plurality of blocks is greater than the number of blocks accessible by the external address signal.

Electrically erasable and programmable semiconductor memory device

A semiconductor memory device includes a memory cell array, a data readout circuit, a decoder circuit and an address transition detecting circuit which detects an address transition of an input address signal and which generates an address transition detection pulse. A redundancy circuit determines whether or not the input address signal indicates a defective memory cell and outputs a redundancy signal to the decoder so that the decoder selects one redundant memory cell in place of the specified defective memory cell. A pulse generator generates a pulse signal having a pulse duration time sufficient to reset the memory cell array and the data readout circuit before reading data from the memory cell array in a case where the redundancy circuit outputs the redundancy signal. The pulse duration time of the pulse signal starts from a time when the address transition detecting circuit generates the address transition signal.

Semiconductor memory device having redundant memory cells

A programmable logic device includes: a programmable AND array; an OR array operatively connected to the AND array; a plurality of external terminals; and a plurality of cell blocks operatively connected to the AND array and OR array and provided for each of the plurality of external terminals, each receiving two output signals from the OR array and outputting a signal to a corresponding external terminal based on the two output signals. By controlling an input/output of an input signal and an internally produced signal and a feedback thereof to the AND array, it is possible to realize various logic constitutions and develop a degree of freedom of the logic design in the entire device.

Programmable logic device having expanded logic capability

A voltage supply level detecting circuit comprising a P-channel MIS transistor and an N-channel MIS transistor, the P-channel and N-channel MIS transistors being connected in series between the variable voltage supply and ground, and the gates of the P-channel and N-channel MIS transistors being connected to a fixed voltage supply.

Voltage supply level detecting circuit

A semiconductor memory device includes a redundancy decoder circuit. The redundancy decoder circuit includes FAMOS transistors to which an address pattern, corresponding to an address of a defective memory cell to be replaced by a redundancy memory cell, is written at the floating gates of the FAMOS transistors. The FAMOS transistors are depletion type. Control gates thereof receive a voltage having ground level or lower during a usual memory access mode.

Semiconductor memory device

An output circuit of a semiconductor device for suppressing erroneous operation due to potential variations of the power supply line or the ground line. The output circuit comprises an output stage inverter connected between the power supply line and the ground line and a clamping circuit for clamping the voltages applied to the output stage inverter. A large instantaneous current which flows through the output stage inverter during a transition of state is greatly suppressed so that erroneous operation is prevented.

Output circuit of a semiconductor device

A semiconductor device includes a first circuit (C1, C1') driven by a first power supply (V.sub.cc) and a second circuit (C2) driven by a second power supply (V.sub.pp) which has a higher potential than the first power supply. A P-channel transistor (Q.sub.18) is provided on the input side of the second circuit and is controlled by the feedback of an output of the second circuit. The P-channel transistor has a source connected to the second power supply. In addition, two N-channel transistors (Q.sub.19, Q.sub.20) are connected in series between the output of the first circuit and the input of the second circuit. Each of the N-channel transistors has a gate, connected to the first power supply and the second power supply, respectively.

CMIS Level shift circuit

A semiconductor memory device wherein each word-line selecting and driving circuit output is connected to a set of plural adjacent word lines and a plurality of memory cells are arranged between one of the adjacent word lines in one set and one of bit lines. By connecting a set of plural adjacent word lines to each word-line selecting and driving circuit the interval between adjacent bit lines, the interval between adjacent word lines, the size of the memory cell array, and therefore the size of the semiconductor memory device can be reduced.

Semiconductor memory miniaturized by line groups and staggered cells

A decoder circuit, used, for example, in a semiconductor memory device, decodes an n bit address signal and selects one of 2.sup.n output lines such as word lines or bit lines. In the decoder circuit, MIS transistors connected to decoded signal output lines are commonly used by adjacent decoded signal output lines, so that the area occupied by the decoder circuit is decreased and the degree of integration is increased.

MIS Decoder circuit

An oscillation circuit for providing an oscillation output having a duty ratio different from 50%. The oscillation circuit is adapted to control, for example, a bootstrap circuit included in an EPROM which is erasable by means of ultraviolet rays. The oscillation circuit is comprised of a depletion type MOS transistor used as a resistance in each CR time constant circuit; the gate and the drain or the gate and the source of each depletion type MOS transistor being connected together and the oscillation circuit comprising a delay circuit having its output positively fed back to its input.

Delay circuit oscillator having unequal on and off times

A semiconductor memory device includes in its chip a decoder circuit which receives external selection signals for selecting a memory chip. The decoder circuit performs the selection of the memory chip in accordance with a logic corresponding to the combination of the external selection signals. The selection logic can be changed by the user of the semiconductor device.

Semiconductor memory device with decoder for chip selection/write in

A semiconductor PROM device comprising a plurality of word address decoders, each of the word address decoders having a decoder section and a high potential voltage supplying section including a transistor. The transistor is connected between one of the word lines and a high potential voltage source and is turned on when programming is effected. The semiconductor PROM device further comprises a plurality of gated program signal generators each of which is supplied with a part of input address signals for selecting a block of a plurality of the word address decoders. Each of gated program signals from the gated program signal generators is applied to the gate electrode of the transistor of the word address decoder whose input address signals include part of the input address signals supplied to the gated program signal generator.

Semiconductor PROM device

An oscillation circuit for providing oscillation frequencies which vary in response to the intensity of incident light rays. The circuit comprises a capacitance for storing charges and a charging circuit; said stored charges being decreased in response to an increase in the intensity of light rays incident on the capacitance; the charging circuit connected to the output of the oscillation circuit; the charging circuit being adapted to charge the capacitance. The oscillation circuit, when adapted to a bootstrap circuit in an EPROM erasable by means of ultraviolet rays, improves the write-in efficiency thereof.

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Tokyo, Japan

Mitsuo Higuchi