Nec Corporation

Mitsuo Baba

Yasushi Aoki

Atsushi Katayama

Masaki Sato

Minoru Kayano

Kiyoshi Mikami

Hiroki Teramoto

Yuuji Takahashi

Masaki Satoh

Satoko Murakami

A phase comparator has a flip-flop circuit and a logic circuit. The flip-flop circuit compares an input clock signal with a leading edge and a trailing edge of an input data signal to produce a leading phase comparison result signal indicative of a leading phase comparison result related to the leading edge of the input data signal and a trailing phase comparison result signal indicative of a trailing phase comparison result related to the trailing edge of the input data signal. The logic circuit produces an output up signal when both of the leading and the trailing phase comparison result signals indicate a lag phase of the input clock signal. The logic circuit produces an output down signal when both of the leading and the trailing phase comparison result signals indicate a lead phase of the input clock signal.

Phase comparator having a flip-flop circuit and a logic circuit

A digital control variable delay circuit includes n amplitude control units which are connected in parallel and each of which receives a pair of input clock signals to be supplied to a differential pair and receives m-bit digital control signals, and a waveform shaping unit which is connected to the outputs of the n amplitude control units. Each amplitude control unit is capable of varying the amplitude of each of the pair of clock signals into (m+1) values using the m-bit digital control signals, and outputs a pair of amplitude-varied clock signals. The waveform shaping unit receives a pair of added clock signals obtained by adding and combining the pairs of amplitude-varied clock signals outputted from the n amplitude control units and outputs a pair of resultant clock signals as output signals.

Digital control variable delay circuit which is hardly susceptible to noise

A digital PLL (phase locked loop) circuit includes a sampling circuit, a plurality of internal circuits and an output switching circuit. The sampling circuit samples a burst data signal in response to a multi-phase clock signal to produce N (N is a positive integer larger than one) sampled data signals. The multi-phase clock signal includes N clock signals, each of which has substantially the same frequency as the data signal and which have phases different by a predetermined component from one after another. Each of the plurality of internal circuits is selected in response to a first selection signal, and outputs a set of a selected one of the N clock signals and an identified data signal from the N sampled data signals, which corresponds to the selected clock signal, in response to the selected clock signal, when the internal circuit is selected. The output switching circuit selects the set corresponding to the selected internal circuit from among the sets from the plurality of internal circuits based on a second selection signal.

Digital PLL circuit operable in short burst interval

A bit synchronization device which extracts an output data signal and an output clock signal from an input data signal on the basis of a multi-phase clock signal. The bit synchronization device is provided with a processing circuit which holds a phase corresponding to a change point of an input data signal with a multi-phase clock signal, and while the input data has a phase without change point, carrying out a data identification free from an error by selecting a clock signal corresponds to the phase without change point.

Bit synchronization method and bit synchronization device

An input data signal is digitally sampled by a data sampling section using an N-phase clock signal including N clock signals whose frequencies are almost the same as the bit rate of the input data signal and whose phases has been successively shifted by 1/N of the clock cycle, and thereby a parallel sample data signal including N sample data signals is obtained. An edge point detection operation section detects edge points in the N sample data signals in one cycle of an extracted clock signal and outputs an edge point operation output signal. A clock signal extraction section selects a clock signal from the N-phase clock signal based on the information of the edge point operation output signal and outputs the selected clock signal as the extracted clock signal. A delay section delays the N sample data signals of the parallel sample data signal and thereby outputs a parallel delayed sample data signal including N delayed sample data signals. A data regeneration section selects a delayed sample data signal from the N delayed sample data signals based on the information of the edge point operation output signal and outputs the selected delayed sample data signal as a regenerated data signal. Due to the delay by the delay section, extraction time of the digital PLL circuit can be decreased to 0 without enlarging the overhead in the input data signal.

Digital PLL circuit and signal regeneration method

Duty measuring circuitry of the present invention includes a pulse detecting circuit for detecting at least one of a convex pulse width and a concave pulse width included in an input data signal. A duty decision circuit determines whether or not the convex pulse width or the concave pulse width detected is smaller than a preselected value. If the detected pulse width is smaller than the preselected, the duty decision circuit determines that the pulse width is valid, and feeds it to an averaging circuit. The circuitry obviates the need for an exclusive fixed pattern, e.g., ONEs and ZEROs alternating with each other customarily used for the measurement of a duty. In addition, the circuitry is capable of accurately measuring a duty even with a random pattern based on RZ (Return-to-Zero) code or NRZ (Non-Return-to-Zero) code.

Circuitry and method for duty measurement

A bit synchronization circuit extracts the central phase of an eye opening irrespective of a jitter distribution of input data to maintain an optimum timing adjustment margin. The bit synchronization circuit has a data edge detector for comparing the phases of an edge of the input data and m-phase clock signals divided from a reference clock. Data edge phase information from the data edge detector is accumulated by a phase accumulation register, which stores the jitter distribution of the input data as accumulated phase information. Based on the accumulated phase information, an eye center phase calculator decodes the negative and positive ends of a jitter range as negative jitter range information and positive jitter range information, and calculates a phase control direction in relation to an extracted phase value which represents a presently selected clock phase. A correction circuit extracts the positional relationship between a present eye opening width and the extracted phase value, and clears the accumulated phase information to increase the eye opening width.

Bit synchronization circuit

A digital PLL circuit includes a sampler which samples a burst data signal depending on N phase clock signals to produce N phase sampled data signals. Based on the N phase sampled data signals, an edge phase detector detects edge information and a duty detector detects duty information signals in synchronization with the reference signal. A selector selects an optimal sampled data signal from the N phase sampled data signals depending on the edge information and the duty information, and a retiming section retimes the sampled data signal selected in synchronization with the reference signal.

Digital PLL circuit

A multiphase clock generating circuit having: a clock generating section for generating N-phase clock signals of number N which have a frequency nearly equal to that of input clock signal and whose phases are sequentially shifted by 360 degrees/N; an input side M-division circuit that divides the frequency of the input clock signal by M, outputting a reset signal to the clock generating section; an output side M-division circuit that is fed with a delayed reset signal that the reset signal output from the clock generating section is accompanied with a predetermined delay, and, synchronized with the delayed reset signal, divides the frequency of output clock signal output from the clock generating section by M; and a controller for comparing the input side M-division clock and the output side M-division clock, and controlling a delay amount of the clock generating section based on the comparison result.

Circuit and method for generating multiphase clock

In a data synchronization circuit for obtaining a clock synchronized with bits of received data to submit the received data to retiming, it is achieved that a phase synchronization without use of a feedback loop configuration giving rise to oscillations is performed. The received data are devided according to the frequency in a frequency dividing circuit. This frequency divided output and the respective n-phase clocks are compared in phase to generate a specific signal to specify one of n-phase clocks having predetermined phase relations to the frequency divided output. While, on the other hand, the change points of the frequency divided output are synchronized with the extracted clock of a clock selector to average the specific signal with the timing of this change point synchronization signal. One of n-phase clocks is extracted in conformity with the state of this averaged output to make an extracted clock and to subject the received data to retiming in a flip-flop by using this clock.

Received-data bit synchronization circuit

In a bit synchronizing circuit, the oscillating operation is prevented in the phase synchronizing stage such that even the reception data including a phase variation such as a jitter component can be appropriately reproduced. A phase comparator compares the phase of reception data with that of each of the n-phase clock signals to produce clock phase information. An averaging circuit obtains mean value data of the clock phase information. D-type flip flop circuits achieve sampling operations of the reception data and latch therein n sampling data items to be thereafter outputted. A data selector selects one of the n sampling data items according to the mean value data of clock phase information and delivers therefrom the selected item as selection data. A clock selector selects one of the n-phase clock signals in association with the average data of clock phase information and then outputs the selected item as an extraction clock signal.

Bit synchronizing circuit

A phase locked loop comprises a voltage controlled oscillator, a 1/n frequency demultiplier, a phase comparator, and a modulation circuit. The phase comparator is supplied with a first signal which varies according to a reference clock signal and a second signal which varies according to a feedback signal supplied from the 1/n frequency demultiplier, executes phase comparison between the two signals, and controls the oscillation frequency of the voltage controlled oscillator by varying a control voltage by outputting an up-control signal or a down-control signal depending on phase difference between the signals. The modulation circuit generates the first signal by periodically modulating the reference clock signal with a shift width which is larger than the dead zone width of the phase comparator, and supplies the phase comparator with the first signal. Preferably, a 1/2 delay circuit is provided between the 1/n frequency demultiplier and the phase frequency comparator, for delaying the feedback signal by half the shift width. According to the phase locked loop, perfectly linear characteristic around the stationary state and elimination of stationary phase difference are realized.

Phase locked loop

A digital PLL circuit has a data sampling circuit for sampling input data in response to N phase clocks in the direction of time. The phase of the clock corresponding to, among the sampled data, the data in which edges are evenly detected is used as a first phase or reference clock. The successive clocks following the first phase clock are used as a second phase clock to an N-th phase clock. The sampled data are rearranged in synchronism with the first phase clock to the N-th phase clock to turn out first phase to N-th phase sampled data. The first phase to the N-th phase sampled data are latched by the first phase clock. The pattern of data received in bursts is identified every period on the basis of the latched first to N-th phase data. Among the latched first to N-th sampled data, the data to be identified are selected. These data are retimed in synchronism with the first phase clock so as to output a phase clock signal.

Digital phase locked loop circuit

A plurality of clock signals at an identical frequency but with different phases are oscillated by a voltage-controlled oscillator beforehand, and selection is made of one of the clock signals whose phase is closest to that of the data signal each time the data signal rises. In parallel with the selection of phase, a phase/frequency comparison is made between any one of the clock signals output from the voltage-controlled oscillator and the selected clock signal. After the comparison, the oscillation frequency of the voltage-controlled oscillator is converted for their matching. This matching allows acquisition of a clock signal with the closest phase immediately after arrival of the data signal, and acquisition of an extraction clock signal with the frequency and phase matched in a short time by parallel conversion of the oscillation frequency of the voltage-controlled oscillator.

Clock signal extraction apparatus using VCO having plurality of

A variable delay buffer circuit composed of a cascade of variable delay buffers, which realizes a delay in response to a delay control signal without any glitches. The delay buffers each have a selector circuit for selecting one of an input signal and a delayed signal produced by delaying in time the input signal in response to a delaying information. The delay buffers each contains a first control means and an output means. The first control means controls a timing of a input of the delaying information into the selector circuit in response to an external control signal. The output means outputs the control signal to by synchronized with an output signal from the selector circuit. Preferably, the first control means contains a latching means for latching the delay information and a second control means for controlling a timing in output of the delay information from the latching means in response to the control signal.

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Tokyo, Japan

Mitsuo Baba