Hitachi, Ltd.

Hitachi Microcomputer System, Ltd.

Mitsuo Asai

Takehisa Hayashi

Yoshihiro Takiyasu

Noboru Masuda

Kenichi Ishibashi

Toshio Doi

Masayoshi Yagyu

Minoru Yamada

Takeshi Onodera

Moritoshi Yasunaga

Katsunari Shibata

Hirofumi Yamashita

Koichi Morita

Tomoyuki Ishida

Ryuichi Ohno

Atsushi Saito

Akira Yamagiwa

Masaru Ohki

Akira Masaki

Koichi Shibata

Hisao Ogata

Toshihiro Okabe

Yuji Sato

Masaru Igawa

Miho Iwanaga

Tatsuo Okahashi

Keiji Moki

Takahiro Sakaguchi

Nozomu Hirose

Hiroshi Takayanagi

Masashi Hashimoto

Mikiko Sato

Yuzo Hirai

Tatsuo Ochiai

Yoshihiro Kuwabara

A video displaying method of displaying, on a display unit, contents of video files. Each of the video files is composed of a plurality of images. The video displaying method includes the steps of extracting, from one of the video files, a plurality of images at predetermined intervals from the images composing the video file; displaying the extracted images on the display unit; in response to a selection of one image from the displayed images, reproducing the video file including the selected image beginning at a position of the selected image in the video file; and displaying the reproduced video file on the display unit.

Video searching method, apparatus, and program product, producing a group image file from images extracted at predetermined intervals

A video searching method, and apparatus, having a function of representing a video file are provided such that the contents of video files stored in a storage device may be recognized definitely and rapidly. The video searching apparatus includes a computer, a storage device, a device for controlling them, and a display device. The apparatus includes a software resource for producing a group image formed of at least two still images of scenes representing the contents of each of video files stored in the storage device. In the apparatus, the size of the group image is changed at any time. In response to manipulation of the group image, file operation such as deletion, movement or name change of a corresponding video file is performed.

Video searching method and apparatus, video information producing method, and storage medium for storing processing program thereof

In a method of increasing the network use efficiency of computer communication and reducing the limitation of byte stream in a transmit/receive request, a virtual circuit is established between protocol modules such as applications for providing the communication function between software to mate one transmit request with one receive request. By returning an acknowledgement in a unit of request, any vain acknowledgement can be avoided and even in the case of asynchronous transmission/reception, a request which is completed in transmission/reception can be ended immediately, thus permitting efficient data transfer. Even when the transmit request length and the receive request length differ from each other, reliable communication of a request having a smaller request length can be ensured between mating transmit and receive requests. Further, in the case of synchronous transmission/reception, by copying only the latter half of a transmission buffer and returning a virtual ACK to the transmitting side when reception of the former half ends, the acknowledgement need not be waited for, thus permitting efficient data transfer.

Communication method with attaching identifiers to receive request and

When an access request is generated from a client in a network file server comprising a computer including a communication controller connected to at least one client through a network and transferring information on a plurality of addresses inside a main storage device as one packet to at least one client, the main storage device having a buffer, a central processing unit and an input/output bus for mutually connecting the communication controller, the central processing unit and the main storage device, and a secondary storage device connected to the computer, an area for storing the data corresponding to this access request is allocated into the buffer of the main storage device. The data corresponding to the access request is read out from the secondary storage device, is transferred to the buffer and is stored in the allocated area. A header for the data in the allocated area in the buffer, the address and size of the header and the address and size of the data are generated in the main storage device on the basis of the access request. As the address and size of the header and the address and size of the data are reported to the communication controller, the data inside the allocated area in the buffer are transferred as one packet to at least one client by the communication controller.

Computer network system for packet-transferring data between computers,

In a video storage and delivery apparatus and corresponding system, video data items are simultaneously supplied to a plurality of users while guaranteeing the time axis and the picture quality of the video data. The apparatus includes a frame address table which indicates a storage location in the apparatus of each frame of video data to start a special reproduction or a reproduction at a desired frame and a control unit controlling a switch bus connecting a plurality of video storage and delivery apparatuses to a plurality of channels so as to conduct data transfers via the switch bus between the apparatuses and between video reproduction devices of the users. From an optical disk data storage storing video data, a plurality of video data items are read in a timesharing fashion to be temporarily stored in a magnetic disk device or a semiconductor memory, thereby delivering the video data items therefrom to the users.

Video storage and delivery apparatus and system

An information processing apparatus is composed of an input layer, a hidden layer and an output layer, and performs a computation in terms of neuron models. In the information processing apparatus, a forward network comprising the input layer, the hidden layer and the output layer executes a computation for externally input data to determine the values of outputs therefrom, and a backward network comprising the output layer and the hidden layer executes computation for output values expected for given inputs to determine learning signal values. The information processing apparatus transfers the output values and learning values between the forward network and the backward network to modify the synapse weights of the neuron models.

Information processing apparatus

A general neuro-computer and system using it is capable of executing a plurality of learning algorithms, providing an instruction execution speed comparable with a hard wired system, and practically neglecting a time required for rewriting microprograms. The neuro-computer is constituted by a neuron array having a plurality of neurons, a control storage unit for storing microinstructions, a parameter register, a control logic, and a global memory. A host computer as a user interface inputs information necessary for the learning and execution of the neuro-computer to the system, the information including learning algorithms, neural network architecture, the number of learnings, the number of input patterns, input signals, and desired signals. The information inputted from the host computer is transferred via a SCSI to the neuro-computer to perform a desired neural network operation.

Neuro-computer system for executing a plurality of controlling algorithms

A semiconductor integrated circuit device is provided which include a plurality of cell columns each having a number of unit cells previously fabricated on a semiconductor substrate selected from the plural kinds of unit cells which are formed in desired circuits by electrically connecting circuit devices previously arranged. Each column includes at least one kind of unit cell of a dynamic circuit which has a node in a floating state during the operation of the cell unit. A fixed potential shield layer is also provided on the cell columns so as to cover the nodes of the dynamic circuits. By virtue of this, a wiring area for electrically connecting the desired cell units can be located between the cell columns and above the shield layer. In other words, signal wirings in the wiring area can pass over the nodes of the dynamic circuits. without adverse parasitic effects. The unit cell can also be provided with a precharge circuit comprising a standard cell and an in-cell wiring layer. Further, clock input terminals of the unit cells which are provided with a precharge circuit can be divided into plural groups, with all of said clock input terminals belonging to the same group and having equal load capacitances being connected. Clock buffer cells can be provided for supplying clock signals to the clock signal wirings for each group.

Semiconductor integrated circuit apparatus and method for designing the

An information processing apparatus which includes an input layer, a hidden layer and an output layer, and performs a computation in terms of models of neurons. A forward network, having the input layer, the hidden layer and the output layer, executes a computation for externally input data to determine the values of outputs therefrom, and a backward network, having the output layer and the hidden layer, executes computation for output values expected for given inputs to determine learning signal values. The information processing apparatus transfers the output values and learning values between the forward network and the backward network to modify the synapse weights of the neuron models.

An information processing system includes a plurality of functional blocks (neurons) and a data bus for transmitting in common the outputs of the individual functional blocks (neurons). Data transaction among the functional blocks (neurons) is performed through the data bus on the time-division basis. For preventing the outputs from conflicting or competition, addresses are assigned to the individual blocks (neurons), respectively, so that only the functional blocks (neuron) having the own address designated by the address signal supplied through an address bus outputs data signal onto the data bus, while the other functional blocks (neurons) receive the information on the data bus as the signal originating in the functional block whose address is designated at that time point. The addresses are sequentially changed. During a round of the address signals, data are transmitted from given functional blocks (neurons) to other given functional blocks (neurons).

Information processing system

This invention discloses a clock distribution system which distributes a first clock signal as a reference clock as the reference for the phase and frequency to each processing unit (e.g. LSI) and generates a multi-phase second clock signal to be used in each processing unit by a delay circuit group whose delay time is adjusted. The clock distribution system comprises a clock generation block for generating a one-phase reference clock; a first control loop for comparing the phase of the reference clock with the phase of a feedback signal and adjusting the phase of the reference clock so that their phases are in agreement; and a second control loop including a delay circuit group consisting of a plurality of variable delay circuits to which the reference clock phase-adjusted by the first control loop is inputted and which are connected in series, and means for generating a multi-phase clock signal by use of the output signal of each of the plurality of variable delay circuits and the phase-adjusted referencde clock, controlling the delay time of the plurality of variable delay circuits so as to accomplish a predetermined relation with the period of the phase-adjusted reference clock and applying one of the multi-phase clock signals as the feedback signal described above to the first control loop.

High speed clock distribution system

A dynamic semiconductor logic circuit comprising a MOS FET logic section for effecting a high-speed logic operation in response to input logic signals after precharging of an output mode and internal nodes the logic section, a CMOS/BiCMOS output buffer section for outputting a result of the logic operation, and a noise suppression section for preventing erroneous operations without sacrificing the high-speed operation characteristic. The circuit, which is fabricated with 0.5-.mu.m-rule technology and operates at high speed with a low-voltage power source of 4.5 V or less, has a precharging section for precharging the output node and internal nodes of the MOS FET logic section and a noise suppression section for latching the output node of the logic section to the source potential by feeding back the output of an output buffer section in order to enlarge the soft error margin. The latching current is held at less than a predetermined ratio to maintain the high-speed operation characteristic.

Semiconductor logic circuit with noise suppression circuit

Growing community of inventors

Kokubunji, Japan

Mitsuo Asai