Renesas Electronics Corporation

Epoch Microelectronics, Inc.

Mitsunori Samata

Satoru Yamamoto

Toshiya Uozumi

Keisuke Ueda

Aleksander Dec

Ken Suyama

Russell P Mohn

In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.

PLL circuit with improved phase difference detection

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Tokyo, Japan

Mitsunori Samata