Fujitsu Corporation

Mitsunori Abe

Takahiro Kitagawa

Ryo Kanai

Kiyoyuki Hatanaka

Shigeo Iriguchi

Nobuo Taketomi

Shigeru Sugino

Akiko Matsui

Naoki Nakamura

Takashi Fukuda

Yoshiyuki Hiroshima

Yoshikazu Hirano

Tetsuro Yamada

Kohei Choraku

Kazuki Takahashi

Rie Takada

Kenichiro Tsubone

Hidehiro Mishiro

Yoshio Kobayashi

Sotaro Kobayashi

A specific conductivity measurement method includes: performing first measurement to obtain a resonance frequency fthat is outputted to a measuring device when the first and second dielectric flat plates each have a thickness t, and an unloaded Qthat corresponds to the resonance frequency f; performing second measurement to obtain a resonance frequency fthat is outputted to the measuring device when the first and second dielectric flat plates each have a thickness tthat is different from the thickness t, and an unloaded Qthat corresponds to the resonance frequency f; and calculating a specific conductivity &#x3c3;of the copper foil and the first and second conductor flat plates based on an arithmetic equation that includes the resonance frequency the unloaded Q, the resonance frequency f, and the unloaded Q.

Specific conductivity measurement method, recording medium recording specific conductivity calculation program, and specific conductivity measurement system

A recording medium recording a program for a process, the process includes: calculating an amount of distortion in a via of a printed circuit board based on an expression using coefficient m, &#x394;&#x3b5;={(L&#xd7;&#x3b1;&#xd7;&#x394;t&#xd7;E)/(D&#xd7;T)}&#xd7;m, where &#x394;&#x3b5; is the amount of distortion, L is a length of the via, &#x3b1; is a thermal expansion coefficient of a base material, &#x394;t is a temperature change of an environment, E is a Young's modulus, D is a diameter of the via, and T is a thickness of plating in the via; and calculating a lifetime of the via based on an expression, M=N/(n&#xd7;365), where M is the lifetime of the via, n is a frequency of the temperature change, and N is the number of cycles of the lifetime satisfying an expression N=C/&#x394;&#x3b5;.

Recording medium recording via lifetime calculation program, via lifetime calculation method, and information processing device

A method of manufacturing a through hole of a substrate includes forming, to the substrate, a cutting hole surrounding a removal-target-part such that a connection part of the substrate remains, the connection part that connects the removal-target-part that is removed from the substrate and a remaining part other than the removal-target-part that has been removed, along a cutting line of the through hole formed to the substrate; applying plating on an area including an inner peripheral wall face of the cutting hole of the substrate; applying a film covering an opening of the cutting hole on a surface of the substrate applied with the plating and performing exposure and development of the film to form an etching resist covering an area including the opening of the cutting hole; performing etching of the plating applied on the substrate; removing the etching resist; and cutting the connection part to remove the removal-target-part.

Method of manufacturing through hole of substrate

An information processing device includes a processor that calculates a distortion amount that represents an amount of distortion generated in a via of a printed circuit board based on a following equation, &#x394;&#x3b5;={(L&#xd7;&#x3b1;&#xd7;&#x394;t&#xd7;E)/(D&#xd7;T)}&#xd7;m&#xd7;&#x3b2;&#xd7;&#x3b3;&#xd7;&#x3b7;; calculates a lifetime of the via based on a following equation, M=N/(n&#xd7;365); changes, when the calculated lifetime is outside a first setting range, at least two design values of the via length, the thermal expansion coefficient, the Young's modulus, the via diameter, or the plating thickness within a second setting range corresponding to the at least two design values respectively; gives points of two perspectives affected by the change and outputs a graph that indicates an impact degree according to the points of the two perspectives for each combination of the at least two design values.

Method for outputting impact degree and information processing device

A wiring board includes, a base plate that has a first surface, a second surface opposite to the first surface, and a side surface coupled to the first surface and the second surface, a conductor provided on the side surface, and a protrusion provided over the side surface. The protrusion partitions the conductor into a first portion on the side surface that extends to the first surface and a second portion on the side surface that extends to the second surface. The protrusion has a solder wettability lower than the conductor and protrudes from the conductor.

Wiring board, electronic apparatus, method for attaching sheet metal covers, and method for manufacturing wiring board

A method for inspecting a laminated board, includes: performing a reflow process to solder an electronic component to a surface of a laminated board in which at least one of a plurality of wiring layers which are laminated with each other is coupled to another adjacent wiring layer via a via; and inspecting, in the reflow process, a conduction state of the via after a temperature of the laminated board reaches a melting point of a solder, and when the temperature of the laminated board is at a temperature range lower than the melting point and higher than room temperature.

Inspection method of laminated board, inspection module, and pallet

A substrate includes an insulation layer including a glass cloth impregnated with a resin, and a through hole having a hole included in the insulation layer and plating formed in an inner surface of the hole, where a location, intersecting with the glass cloth, of an outer circumferential portion of the through hole has a recessed portion recessed toward an outside of the hole.

Substrate and method of manufacturing the same

Disclosed substrate with embedded component includes: an insulating base member; a conductive pad formed on the insulating base member; a component connected to the conductive pad with a solder; and a resin covering the component, wherein a hole is provided in the insulating base member and the conductive pad, and the insulating base member is exposed on a side surface of the hole.

Substrate with embedded component

An electronic component analyzing apparatus is provided with a fixing part configured to hold a substrate to which an electronic component is soldered; a gripper configured to grip the electronic component; a transmission part coupled to the gripper, and configured to transmit an external force to the gripper as a force acting in a direction away from the substrate; and a support part configured to pivotally support the transmission part.

Electronic component analyzing apparatus and method

A printed circuit board on which a surface mount electronic device is mounted. The printed circuit board includes a substrate on which land arrangements are disposed in an array. Each land arrangement includes a core portion and drawing portions. The drawings are disposed along diagonal directions relative to the core portions of the array of the land arrangements.

Printed circuit board and printed circuit board unit

A printed circuit board provided with board electrodes, wherein each board electrode is provided with a board electrode base, for carrying by soldering a bottom electrode arranged at a bottom of an electronic device inside from outer edges of the electronic device, arranged inside from the outer edges of the electronic device and a projection projecting out from the board electrode base, narrower in width than the board electrode base, and connected to an interconnect of the printed circuit board.

PCB with soldering pad projections forming fillet solder joints and method of production thereof

A laminate capacitor circuit board which permits constants of various kinds of circuit elements to be set by selectively effected connections between wiring layers, and a laminate capacitor circuit board which permits distributed circuit constants in a high-frequency wiring layer sandwiched between two shielding wiring layers to be set as desired. These circuits are formed with at least a pattern of a conductive foil on each dielectric layer, and include a plurality of wiring layers laminated one upon another, a wiring layer for connections laminated to a surface of the plurality of wiring layers laminated one upon another, a plurality of terminal patterns formed on the wiring layer for connections in a state insulated from each other, a plurality of vias for electrically connecting at least two of the plurality of terminal patterns to corresponding ones of the plurality of wiring layers, and connecting means for selectively connecting the plurality of terminal patterns to each other.

Growing community of inventors

Kawasaki, Japan

Mitsunori Abe