Micron Technology Incorporated

Elpida Memory, Inc.

Nec Corporation

Ps4 Luxco S.a.r.l.

Mitsunari Sukekawa

Sanh D Tang

Hiroaki Taketani

Christopher John Kawamura

Kirk D Prall

Takeshi Watanabe

Akira Hoshino

Masayuki Hamada

Yasutaka Iuchi

Yusuke Yamamoto

Hiroshi Toyama

Yoshitaka Nakamura

Kenichi Sugino

Keisuke Shimada

Shogo Omiya

Yoshinori Ikebuchi

Yasutaka Okada

Hiroyuki Uno

A semiconductor memory device including an access transistor configured as a vertical transistor comprises a channel portion and a pair of source/drain regions; a storage capacitor connected to one of the pair of source/drain regions; a bit line connected to the other of the pair of source/drain regions, a first semiconductor layer provided in the source/drain region to which the bit line is connected. Preferably, the first semiconductor layer comprises SiGe.

Semiconductor memory device and method of forming the same

Microelectronic devices include at least one memory cell, each with six transistors collectively comprising six pillars grouped in pillar pairs and formed from a semiconductor material. Each of the pillar pairs includes a first and a second pillar. Gate electrodes are also included, with each gate electrode extending between and horizontally around a portion of the first pillar and a portion of the second pillar of a respective one of the pillar pairs. Conductive structures are electrically coupled to the six pillars. At least one of the conductive structures is in physical contact with more than one of the pillars of the microelectronic device. Related methods and electrical systems are also disclosed.

Compact microelectronic 6T SRAM memory devices, and related systems and methods

Apparatuses and methods for manufacturing semiconductor memory devices are described. An example method includes: forming a conductive layer and sputtering the conductive layer with gas. The conductive layer includes a first portion having a top surface having a first height; and a second portion having a top surface having a second height lower than the first height. Sputtering the conductive layer with gas may be performed to remove the first portion of the conductive layer and increase the second height of the second portion of the conductive layer concurrently.

Conductive layers in memory array region and methods for forming the same

Bit line noise suppression and related apparatuses, methods, and computing systems are disclosed. An apparatus includes a complementary metal-oxide-semiconductor (CMOS) wafer and a memory cell wafer. The CMOS wafer includes CMOS wafer contact pads and sense amplifier circuitry electrically connected to some of the CMOS wafer contact pads. The memory cell wafer includes memory cell wafer contact pads and bit lines electrically connected to some of the memory cell wafer contact pads. The bit lines include primary bit lines and secondary bit lines. Each of the secondary bit lines extends in parallel proximate to a corresponding one of the primary bit lines. A cross intersection of a first primary bit line with a first secondary bit line located proximate to a parity intersection of a second primary bit line with a second secondary bit line. The first primary bit line is adjacent to the second primary bit line.

Bit line noise suppression and related apparatuses, methods, and computing systems

An apparatus includes: a memory mat including a plurality of vertical memory cell transistors; a shield structure covering the memory mat and surrounding each of the plurality of vertical memory cell transistors; and a ring-shaped wiring above the shield structure, the ring-shaped wiring being connected to the shield structure in an edge region of the shield structure.

Semiconductor device

An apparatus includes a semiconductor substrate; an access transistor including channel, source and drain regions arranged in a vertical direction to the semiconductor substrate and a gate-electrode facing to the channel region; a storage capacitor coupled to one of the source and drain regions; a bit-line coupled to the other of the source and drain regions; and a pull-out-electrode connected to the bit-line; wherein surfaces of the source and drain regions and the pull-out-electrode on the bit-line side is arranged at substantially the same height from the upper surface of the semiconductor substrate.

Semiconductor device and method of forming the same

An apparatus includes a base structure having a first portion including a plurality of transistors and a second portion surrounding the first portion; a storage structure on the first portion of the base structure, the storage structure including a plurality of storage capacitors each coupled to a corresponding one of the plurality of transistors; an interface structure on the second portion of the base structure; and a peripheral structure on the interface structure; wherein the interface structure is divided into a plurality of insulating films and the plurality of insulating films are arranged away from each other to have a plurality of voids between the second portion of the base structure and the peripheral structure.

An integrated circuit construction comprising memory comprises two memory-cell-array regions having a peripheral-circuitry region laterally there-between in a vertical cross-section. The two memory-cell-array regions individually comprise a plurality of capacitors individually comprising a capacitor storage node electrode, a shared capacitor electrode that is shared by the plurality of capacitors, and a capacitor insulator there-between. A laterally-extending insulator structure is about lateral peripheries of the capacitor storage node electrodes and is vertically spaced from a top and a bottom of individual of the capacitor storage node electrodes in the vertical cross-section. The peripheral-circuitry region in the vertical cross-section comprises a pair of elevationally-extending walls comprising a first insulative composition. A second insulative composition different from the first insulative composition is laterally between the pair of walls. The pair of walls individually have a laterally-outer side of the first insulative composition that is directly against a lateral edge of the insulator structure that is in different ones of the two array regions. Other embodiments, including methods, are disclosed.

Integrated circuit constructions comprising memory and methods used in the formation of integrated circuitry comprising memory

A method of forming an array of capacitors comprises forming a vertical stack above a substrate. The stack comprises a horizontally-elongated conductive structure and an insulator material directly above the conductive structure. Horizontally-spaced openings are formed in the insulator material to the conductive structure. An upwardly-open container-shaped bottom capacitor electrode is formed in individual of the openings. The bottom capacitor electrode is directly against conductive material of the conductive structure. The conductive structure directly electrically couples the bottom capacitor electrodes together. A capacitor insulator is formed in the openings laterally-inward of the bottom capacitor electrodes. A top capacitor electrode is formed in individual of the openings laterally-inward of the capacitor insulator. The top capacitor electrodes are not directly electrically coupled together. Structure independent of method is disclosed.

Array of capacitors, an array of memory cells, a method of forming an array of capacitors, and a method of forming an array of memory cells

Some embodiments include a memory device having a buried wordline, a shield plate, and an access device. The access device includes first and second diffusion regions and a channel region. The diffusion regions and the channel region are arranged vertically so that the channel region is between the first and second diffusion regions. The wordline is adjacent to a first side surface of the channel region, and the shield plate is adjacent to a second side surface of the channel region; with the first and second side surfaces being in opposing relation to one another. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies comprising memory cells and shielding material between the memory cells

A method for forming a multilayer conductive structure includes forming a first conductive portion; forming a second conductive portion containing ruthenium (Ru) therein on the first conductive portion; forming a third conductive portion on the second conductive portion; and performing a silicidation process on the second conductive portion.

A method including forming a first member having a first portion including a plurality of storage capacitors therein and a second portion surrounding the first portion; forming a second member of a concave shape having a third portion, which corresponds to a lower top surface of the concave shape, including a plurality of access transistors provided correspondingly to the plurality of storage capacitors therein and a fourth portion, which corresponds to an upper top surface of the concave shape, surrounding the third portion; stacking the first member on the second member to physically connect the second and fourth portions and have a gap between the first and third portions; cutting the first member to physically separate the first portion from the second portion; and joining the separated first portion and the third portion with filling the gap therebetween.

Method of forming a semiconductor device

Some embodiments include integrated memory having a wordline, a shield plate, and an access device. The access device includes first and second diffusion regions, and a channel region. The channel region is vertically disposed between the first and second diffusion regions. The access device is adjacent to the wordline and to the shield plate. A part of the wordline is proximate a first side surface of the channel region with an intervention of a first insulating region therebetween. A part of the shield plate is proximate a second side surface of the channel region with an intervention of a second insulating region therebetween. The first insulating region includes an insulative material. The second insulating region includes a void. Some embodiments include memory arrays. Some embodiments include methods of forming integrated assemblies.

Growing community of inventors

Hiroshima, Japan

Mitsunari Sukekawa