Tohoku University

Zycube Co., Ltd.

Other

Asahi Glass Company, Limited

Fuji Xerox Co., Ltd.

Tokyo Electron Limited

Toshiba Memory Corporation

Semiconductor Technology Academic Research Center

Tohoku-microtec Co., Ltd.

Mitsumasa Koyanagi

Takafumi Fukushima

Tetsu Tanaka

Masaaki Takata

Nobuaki Miyakawa

Kang-Wook Lee

Yasunori Okano

Masahiko Sugiyama

Kenichi Kawauchi

Tetsuro Kawata

Makoto Motoyoshi

Satohiko Hoshino

Norihiko Kuroishi

Hajime Mushiake

Shinya Kikuta

Reiji Aibara

Hiroyuki Kurino

Jeoung Chill Shim

Norihiro Katayama

Kangwook Lee

A liquid is supplied to a substrate and a chip component is arranged on the liquid. The substrate includes a first surface in which a rectangular mounting region is formed. The chip component includes a second surface having a rectangular shape which substantially coincides with the shape of the mounting region, and has an area substantially equal to that of the mounting region. The mounting region includes first and second regions. Wettability of the first region with respect to the liquid is higher than that of the second region with respect to the liquid. The first region is provided symmetrically with respect to a first central line passing through the middle of a pair of long sides and a second central line passing through the middle of a pair of short sides in the mounting region, and includes rectangular partial regions. The liquid is supplied to the first region.

Method for aligning chip components relative to substrate by using liquid

A semiconductor device includes a metal column that extends in a stretching direction; a polymer layer that surrounds the metal column from a direction crossing the stretching direction; and a guide that surrounds the polymer layer in the crossing direction so as to be spaced from the metal column with the polymer layer interposed therebetween. A method for manufacturing semiconductor devices includes a step of filling a mixture containing metal particles and polymers in a guide; and a step of subjecting the mixture to a heat treatment so that the polymers agglomerate to the guide to form a polymer layer that makes contact with the guide and the metal particles agglomerate away from the guide with the polymer layer interposed therebetween to form a metal column that stretches in a stretching direction of the guide from the metal particles.

Semiconductor device and method for manufacturing the same

To miniaturize metal columns. A semiconductor device includes a metal column () that extends in a stretching direction; a polymer layer () that surrounds the metal column from a direction crossing the stretching direction; and a guide () that surrounds the polymer layer in the crossing direction so as to be spaced from the metal column with the polymer layer interposed therebetween. A method for manufacturing semiconductor devices includes a step of filling a mixture () containing metal particles () and polymers () in a guide (); and a step of subjecting the mixture to a heat treatment so that the polymers agglomerate to the guide to form a polymer layer () that makes contact with the guide and the metal particles agglomerate away from the guide with the polymer layer interposed therebetween to form a metal column () that stretches in a stretching direction of the guide from the metal particles.

The present invention relates to a chip support substrate including a lyophilic regionthat is formed on the substrate and that absorbs a chipA, and an electrodethat is formed on the substrate and in the lyophilic region and that generates electrostatic force in the chip, and to a chip support method including the steps of arranging the chip onto the lyophilic region of the chip support substrate with a liquid, the chip support substrate comprising the lyophilic region that is formed on the substrate, and the electrode that is formed on the substrate and in the lyophilic region, and generating the electrostatic force in the chip corresponding to the electrode by applying a voltage to the electrode.

Chip support substrate, chip support method, three-dimensional integrated circuit, assembly device, and fabrication method of three-dimensional integrated circuit

In a method of fabricating an integrated circuit device having a three-dimensional stacked structured, the step of fixing many chip-shaped semiconductor circuits to a support substrate or a circuit layer with a predetermined layout can be performed easily and efficiently with a desired accuracy. Temporary adhesion portionsof semiconductor chipsare temporarily adhered to corresponding temporary adhesion regionsof a carrier substrateby way of sticky material. The carrier substrateis then pressed toward a support substrate or a desired circuit layer, thereby contacting connecting portionsof the chipson the carrier substratewith corresponding predetermined positions on the support substrate or a circuit layer. Thereafter, by fixing the connecting portionsto the predetermined positions, the chipsare attached to the support substrate or the circuit layer with a desired layout.

Method and apparatus for fabricating integrated circuit device using self-organizing function

There is provided a three-dimensional integrated circuit manufacturing method for temporarily attaching a chip to a transcription substrate, and securely detaching the chip from the transcription substrate when the chip is transferred to a supporting substrate. When a chip is temporarily attached to a transcription substrate, by evaporating a liquid existing between the chip and the transcription substrate, the solids of the chip and the transcription substrate can be attached to each other. Accordingly, the chip can be temporarily attached to the transcription substrate so as not to be deviated from its own position. Further, by setting adhesive strength between the chip and a supporting substrate to be higher than that between the chip and the transcription substrate, the chip can be securely detached from the transcription substrate when the chip is transferred from the transcription substrate to the supporting substrate.

Method and apparatus for manufacturing three-dimensional integrated circuit

In a method of fabricating an integrated circuit device having a three-dimensional stacked structured, the step of fixing many chip-shaped semiconductor circuits to a support substrate or a circuit layer with a predetermined layout can be performed easily and efficiently with a desired accuracy. Temporary adhesion portionsof semiconductor chipsare temporarily adhered to corresponding temporary adhesion regionsof a carrier substrateby way of water films. The carrier substrateis then pressed toward a support substrate or a desired circuit layer, thereby contacting connecting portionsof the chipson the carrier substratewith corresponding predetermined positions on the support substrate or a circuit layer. Thereafter, by fixing the connecting portionsto the predetermined positions, the chipsare attached to the support substrate or the circuit layer with a desired layout.

A brain probe includes: a core probe made from a metal; and n electrode plates attached so as to cover an entire side surface circumference of the core probe and forming n side planes providing an n-angular cross section (n is an integer equal to or greater than 3). Each of the electrode plates is manufactured by a LSI manufacturing process, and provided with at least one electrode and a lead-out wiring extending in a longitudinal direction of a side plane from each of the at least one electrode.

Brain probe and method for manufacturing same

A method of fabricating a semiconductor device having a three-dimensional stacked structure by stacking semiconductor circuit layers on a support substrate, including the steps of: forming a trench in a semiconductor substrate; filling inside the trench with a conductive material to form a conductive plug; forming an element or circuit in an inside or on a surface of the semiconductor substrate where the conductive plug was formed; covering the surface of the semiconductor substrate where the element or circuit was formed with a second insulating film; and fixing the semiconductor substrate to the support substrate or a remaining one of the semiconductor circuit layers by joining the second insulating film to the support substrate or the remaining one of the semiconductor circuit layers through a wiring structure; selectively removing the semiconductor substrate to expose the first insulating film; and selectively removing the first insulating film.

Method of fabricating semiconductor device having three-dimensional stacked structure

A process for producing a nonvolatile semiconductor memory having a mixed or laminated structure of a hardly oxidizable material composed of a hardly oxidizable element having Gibbs' free energy for forming oxide higher than that of Si under the same temperature condition at 1 atm and in temperature range of 0&#xb0; C. to 1,200&#xb0; C. and an oxide of an easily oxidizable material composed of an element having Gibbs' free energy for forming oxide lower than that of Si under the same temperature condition at 1 atm in the temperature range and Si. The process includes forming a portion of the hardly oxidizable material and a portion of the oxide by physical forming method and carrying out heat treatment in oxidizing and reducing gas mixture. The ratio of the gases and the temperature are controlled so that the hardly oxidizable material is reduced and the oxide is oxidized in the temperature range.

Nonvolatile semiconductor memory element excellent in charge retention properties and process for producing the same

A nonvolatile semiconductor memory device which can shorten data writing and erasing time, significantly improve the endurance characteristic and be activated with low power consumption includes an insulating layer with electric insulation, wherein, a charge retention layer formed adjacent to a tunnel insulating film contains nano-particles comprised of a compound which is constituted from at least one single-element substance or chemical compound having a particle diameter of at most 5 nm functions as a floating gate, and which are independently dispersed with a density of from 10to 10particles per square centimeter.

Nonvolatile semiconductor memory device and manufacturing process of the same

A nonvolatile semiconductor memory device including a source region and a drain region formed on a surface of a semiconductor substrate, a channel-forming region formed so as to connect the source region and the drain region or so as to be sandwiched between the source region and the drain region, a tunnel insulating film formed in contact with the channel-forming region, a charge retention layer formed adjacently to the tunnel insulating film, a gate insulating film formed adjacently to the charge retention layer, and a control gate formed adjacently to the gate insulating film. The charge retention layer includes an insulating matrix having, per nonvolatile semiconductor memory device, one conductive nano-particle which is made of at least one single-element substance or chemical compound that functions as a floating gate.

Nonvolatile semiconductor memory device having nanoparticles for charge retention

The semiconductor device is capable of coping with speedup of operation using a low dielectric constant material film other than silicon. The base () formed by the substrate () and the low dielectric constant material film () whose relative dielectric constant is lower than silicon is provided. The semiconductor element layer including the MOS transistor () is adhered onto the surface of the base () for stacking. The transistor () is formed by using the island-shaped single-crystal Si film () and buried in the insulator films (), () and (). The multilayer wiring structure () is formed on the semiconductor element layer and is electrically connected to the transistor (). The electrode () functioning as a return path for the signals is formed on the back surface of the base (). Instead of forming the electrode () on the base (), the electrodes (A) may be arranged on the back surface of the base (A), configuring the base (A) as an interposer.

Method of fabricating semiconductor device using low dielectric constant material film

A nickel-silicon compound forming method is disclosed which comprises forming nickel on at least one of only silicon and a compound containing silicon, and performing stepwise-heating of the nickel together with the at least one of only silicon and the compound containing silicon.

Nickel-silicon compound forming method, semiconductor device manufacturing method, and semiconductor device

A solid-state image sensor has a chip-size package, which can be easily fabricated. The element-formation regions are formed in the semiconductor substrate () of the light-receiving element layer () corresponding to the pixel regions. The semiconductor light-receiving elements (PD) are formed in the respective element-formation regions and covered with the light-transmissive insulator films (), () and (). The light-introducing layer (), which includes the light-introducing cavity () and the quartz cap () for closing the cavity, is formed on the film (). The microlenses () are incorporated into the cavity (). The electric output signals of the semiconductor light-receiving elements (PD) are taken out to the bottom of the substrate () by way of the buried interconnections of the substrate () and then, derived to the outside of the image sensor by way of the output layer () or the interposer (A).

Growing community of inventors

Sendai, Japan

Mitsumasa Koyanagi