Fujitsu Corporation

Mitsuhisa Shimizu

Yasunori Kanai

Kazumasa Nawata

Toshiaki Sakai

Taichi Saitoh

Kenichi Ohno

Tohru Hosomizu

Hiroki Yada

Rokutaro Ogawa

A latch circuit including at least three gate circuits, and a noise resistance circuit. A first gate circuit (3, 4, 11, 16) receives a data signal (DT) and a clock signal (CLK). A second gate circuit (1, 7, 13, 17) is connected to an output of the first gate circuit. A third gate circuit (2, 5, 12 18) receives a first inverted clock signal (CLK) at an input terminal. A second input terminal of the third gate circuit is connected to an output of the second gate circuit and is a first output terminal is connected to an input terminal of the second gate circuit, so that a feedback line is formed between the second and third gate circuits. The noise resistance circuit (8, 9, 20, 21) has at least a signal delay element in the feedback line. The noise resistance circuit may include a filter circuit. The noise resistance circuit may also include an amplifier circuit.

ECL latch circuit having a noise resistance circuit in only one feedback

A semiconductor device such as an ECL gate array having emitter-follower-type output transistors, wherein protective elements are arranged between input/output pads and a power supply line connected to the collectors of the emitter-follower-type output transistors, whereby wiring between the protective elements and the power supply line become unnecessary so that the manufacturing process becomes easy and the integration degree is improved while a large tolerance voltage is maintained against destruction due to static electricity.

ECL gate array semiconductor device with protective elements

An ECL gate array comprising a plurality of basic cells. Each basic cell has a pair of emitter-coupled transistors, and a load connected between the collectors of the transistors and a power supply line. In accordance with a circuit design information, the resistance value of the load can be selected for increasing a noise margin of the output logic levels without deteriorating the switching speed.

ECL gate array with collector resistance compensation for distance from

A large scale semiconductor integrated circuit device comprising plural transistors and resistors formed in one semiconductor substrate, and many emitter-coupled circuits formed by connecting the transistors and resistors with a double metallic layer on the substrate surface. Groups of these emitter coupled circuits are disposed in the form of arrays with circuits of several groups handling larger power than those of other groups, and resistance values in the emitter coupled circuits of the different groups are selected in accordance with the position and arrangement of each group to compensate for any potential variation between that group and the power supply and ground terminals between the groups and respective input/output terminals. Large scale transistors are provided for outputting the emitter-follower circuits. These groups contain the emitter coupled circuits, and are connected to the input/output terminals by the double metallic wiring layer.

Growing community of inventors

Kawasaki, Japan

Mitsuhisa Shimizu