Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Mitsuhiro Yano

Susumu Watanabe

Satoshi Tanaka

Toshiya Kotani

Tomoaki Yabe

Sachiko Kobayashi

Sachiko Kobayasi

Toshiba Kotani

A semiconductor device includes a substrate; a first semiconductor layer above the substrate, a second semiconductor layer between the substrate and the first semiconductor layer, first and second conductors, an electrode, and first and second insulating films. The first and second semiconductor layers have a first end and a second end opposite to the first end. The first conductor is connected to the first ends of the first and second semiconductor layers. The second conductor includes a first portion connected to the second ends of the first and second semiconductor layers and a second portion positioned inside the substrate. The electrode faces portions of first and second semiconductor layers between the first end and the second end thereof. The first insulating film is provided between the first semiconductor layer and the electrode; and the second insulating film is provided between the second semiconductor layer and the electrode.

Semiconductor device

A pattern correction method executed by a computer includes a first correction and a second correction. The first correction is executed by calculating a correction value, in consideration for an optical proximity effect, for edges (first edges) meeting a condition among the edges constituting a designed pattern. Subsequently, The second correction is executed for an edge (second edge) which does not meet the condition, by use of the correction value of any one of the edges (first edges) adjacent to the second edge among the first edges for which the first correction is executed, thus connecting the corrected first edge and the corrected second edge by a line segment. The pattern is corrected to a shape suitable for a mask drawing and a check with simple processing.

Manufacturing method of semiconductor device

Pattern correction method of semiconductor device

A chip division information storage unit configured to register chip division information; a chip layout generation unit configured to generate master mask chip layout information by sequentially allotting sub-patterns to a master mask in an order beginning with the largest from the plurality of sub-patterns; a master mask chip layout information storage unit configured to register the master mask chip layout information; a chip pattern data generation unit configured to generate master mask chip pattern data by referencing the reticle chip pattern data and divide each chip in accordance with the master mask chip layout data; a master mask pattern data information storage unit configured to register the master mask chip pattern data; and a pattern data generation unit configured to generate master mask pattern data by referencing the master mask chip layout information and the master mask chip pattern data, are provided.

Pattern data generation system, method and program for pattern data generation, reticle fabricating method, and semiconductor device manufacturing method using the pattern data

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Kanagawa-ken, Japan

Mitsuhiro Yano