Hitachi, Ltd.

Kokusai Electric Co., Ltd.

Hitachi Communication Technologies, Ltd.

Mitsuhiro Wada

Takahiko Kozaki

Norihiko Moriwaki

Hiroshi Kuwahara

Yoshihiro Kondo

Takayuki Kanno

Arata Nakagoshi

Tetsuo Takemura

Yoshinobu Yamamoto

Shinichi Iwaki

Yusho Futami

Yutaka Fukushima

Yumiko Watanabe

Kaori Nakayama

Isao Shimbo

Mitsuyoshi Hashida

Kouichi Ohta

Hirofumi Udaki

Hiroaki Kasahara

Masao Wanami

Nobuyuki Yamamoto

Yasuo Murakami

Masayuki Takase

Hiroaki Miyata

Hiroaki Nakazawa

Makoto Matsuoka

Masami Takahashi

Takaaki Toyama

Noriyuki Sueyoshi

Akio Makimoto

Yozo Oguri

Masumi Fukano

Yasuo Oginuma

An access server starts the individual collection of communication statistics information on each of LCP sessions upon the establishment of a data link, individually collects communication statistics information on each of NCP sessions established on the LCP session, notifies a RADIUS server of the statistics information on the LCP session when the data link is released, and notifies, when the NCP session is released, the RADIUS server of the statistics information on the released NCP session.

Access server with function of collecting communication statistics information

A traffic shaper comprises a bandwidth controllerhaving a plurality of leaky bucket units-to-n prepared in correspondence with buffer memories-to-n, and an output queue designation unitfor specifying a buffer memory from which a packet is to be read out. Each of the leaky bucket unitshas a level counterfor decrementing the count value at a predetermined rate, and a level increasertofor increasing the count value of the level counter by a value proportional to the product of the length of a transmitted packet and a unitary increment value which is variable depend on the current count value of the level counter.

Leaky bucket type traffic shaper and bandwidth controller

A packet switch having a structure of writing a variable length packet received from each of input lines into a shared buffer memory on a fixed length data block unit basis, wherein a buffer controller forms an input queue for each input line and, when the last data block of a variable length packet is registered in the input queue, links a linked address list for the input queue to one or a plurality of output queues corresponding to one or a plurality of packet destination output lines.

Shared buffer type variable length packet switch

A packet switch which includes input line interfaces for converting variable length packets received from input lines to fixed length cells, a switch unit for switching said packets in cell units, output line interfaces for converting output cells from the switching unit to variable length packets and transmitting the variable length packets over output lines. Each of the input line interfaces has a cell output controller for queuing the fixed length cells for each output line according to the degree of priority of the cells, and for selectively outputting the stored cells in the queues in order of priority, thereby to suppress the transmission of cells with a low priority during the times of congestion.

Packet switch for switching variable length packets in the form of ATM cells

A plurality of address chains are assigned to each of such flows as output lines, priority control, etc. in the address management carried out in a switch with a shared buffer. Each of the address chains has a write address register and a read address register The switch is also provided with a distributive pointer for distributing cells in a flow to a plurality of address chains and a write address register selector as well as a read pointer for reading packets from a plurality of the address chains and a read address register selector so as to read the packets through a pipeline with use of those plural address chains.

Packet switching apparatus with a common buffer

An ATM switch that can be expanded to form a large scale ATM switch with minimal hardware additions. The ATM switch includes a plurality of ATM switch units arranged in parallel, a plurality of cell distributors arranged on the input side of the ATM switch units, and a plurality of cell assemblers arranged on the output side of the ATM switch units. Each of the cell distributors distributes ATM cells received from a plurality of incoming highways to a buffer memory having a plurality of queues corresponding to the output ports of the ATM switch units, namely destinations of the ATM cells, and stores the ATM cells to the queues in the buffer memory. Each cell distributor reads ATM cells having the same destination information, and outputs such ATM cells to respective ones of the ATM switch units in parallel. Each of the ATM switch units independently exchanges the received ATM cell in parallel with the other ATM switch units. Each of the cell assemblers multiplexes ATM cells received from the ATM switch units in a manner to preserve the time sequential order of the ATM cells, and outputs the ATM cells to one of a plurality of outgoing highways. A desired increase in the capacity of the ATM switch is implemented by adding an ATM switch unit between the cell distributors and the cell assemblers, thereby allowing for an increase in hardware in proportion to the desired increase in capacity.

ATM switch

Duplicate optical fibers connect between a base station controller and a radio base station for each route. The duplicate optical fiber is connected to each of the radio base stations for each route through a star coupler. The radio base stations are arranged in each of areas so that the radio base stations for different routes are arranged adjacent to each other.

Portable telephone system

Growing community of inventors

Fujisawa, Japan

Mitsuhiro Wada