Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Ulsi Systems Co., Ltd.

Other

Nippon Telegraph and Telephone Corporation

Hitachi Vsli Engineering Corp.

Mitsuhiro Takano

Hiroshi Yoshioka

Makoto Morino

Shinji Udo

Sinichi Miyatake

Kazuhiko Kajigaya

Masashi Horiguchi

Akira Endo

Ryoichi Hori

Takashi Yamazaki

Kazuyoshi Oshima

Kazuyuki Miyazawa

Jun Etoh

Yuji Sakai

Yasunori Yamaguchi

Tetsurou Matsumoto

Yasuhiro Kasama

Shinichi Ikenaga

Eiji Miyamoto

Manabu Tsunozaki

Jiro Sawada

Hirokazu Saito

Atsushi Kumata

Akihiko Takase

Tsutomu Takahashi

Shinichi Miyatake

Naoaki Yamanaka

Kyoko Ishii

Youichi Sato

Kazuo Mihashi

Toshiya Oouchi

Hiromi Tsukada

Shigeo Shinada

Shouji Wada

Nobuo Komatsu

A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.

Semiconductor memory device and defect remedying method thereof

A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.

A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. This structure in which the peripheral circuits are arranged at the center portion of the chip permits the longest signal transition paths to be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. A benefit of this structure in which the peripheral circuits are arranged at the center portion of the chip, is that the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Semiconductor device formed in a rectangle region on a semiconductor substrate including a voltage generating circuit

Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Semiconductor memory device having zigzag bonding pad arrangement

In an input cell policing method in a network of an asynchronous transfer mode, according to information contained in a header field of each input cell, a group to which the cell belongs is identified. For each group, there are set a plurality of time frames having a predetermined length and mutually different phases to count the number of input cells in each time frame period. For each time frame, the count value of input cells is compared with a predetermined threshold value. An input cell for which the count value exceeds the threshold value in either one of the time frames is assumed to be an excess cell. The excess cell is discarded or a violation mark is added thereto.

ATM cell policing method and apparatus

Growing community of inventors

Tokorozawa, Japan

Mitsuhiro Takano