Mitsubishi Electric Corporation

Mitsubishi Denki Kabushiki Kaisha

Mitsuhiro Shimozawa

Koji Tsutsumi

Akihito Hirai

Ryoji Hayashi

Kenji Itoh

Hiroaki Nagano

Takatoshi Katsura

Yuki Yanagihara

Akira Inoue

Yoshihito Hirano

Yoshinori Takahashi

Tomohiro Akiyama

Kiyohide Sakai

Fumio Ishizu

Noriharu Suematsu

Masaomi Tsuru

Morishige Hieda

Sho Ikeda

Kazutomi Mori

Mitsuru Mochizuki

Yoshinori Matsunami

Hiroyuki Joba

Shinjirou Fukuyama

Takanobu Fujiwara

Shinya Yokomizo

Kenichi Maeda

Seiichi Saito

Tadashi Takagi

Hiroshi Otsuka

Yoshihiro Akeboshi

Wataru Yamamoto

Kenichi Tajima

Kenji Kawakami

Akio Iida

Masayoshi Ono

Hiroyuki Nonomura

Naohisa Takayama

Hifumi Noto

Yuichi Fujimoto

Tatsuya Hagiwara

Yoshinori Tsuyama

Yoshiaki Morino

Youji Isota

Kengo Kawasaki

Yoshinori Yasunaga

A radar device includes a transmission module, a reception module, and a signal processing unit. The transmission module includes an RF signal source that generates a transmission chirp signal synchronized with a reference signal. The reception module includes an RF signal source that generates a reception chirp signal used as a reception local signal and synchronized with the reference signal. The reception module receives a reflected wave of the transmission chirp signal emitted from the transmission module, and mixes a received reception signal with the reception chirp signal. The signal processing unit detects a target based on a beat signal generated by the mixing by the reception module. The signal processing unit controls at least one of the RF signal sources such that between the transmission chirp signal and the reception chirp signal are output at timings shifted from each other, and corrects a change in a phase difference between the transmission module and the reception module, using a phase of a signal of a direct wave from the transmission module to the reception module.

Radar device, control circuit of radar device, and storage medium of radar device

A variable gain amplifier includes a first transistor group which is connected to an input terminal and an output terminal, and which amplifies a signal from the input terminal to output the amplified signal to the output terminal; a second transistor group connected to the input terminal; a third transistor group connected to the output terminal; and a controller configured to control the first transistor group, the second transistor group, and the third transistor group so that a total number of the number of transistors to be turned on in the first transistor group and the second transistor group is kept at a constant value, and total numbers of transistors to be turned on in the first transistor group and in the third transistor group are the same.

Variable gain amplifier

A mixer includes a first unit mixer, a second unit mixer, a third unit mixer, and a fourth unit mixer that have the same configuration and a first combiner, a second combiner, and a third combiner that have the same configuration. The first to the fourth unit mixers each include a differential RF signal terminal. Output of the first unit mixer and output of the second unit mixer are combined by the second combiner. Output of the third unit mixer and output of the fourth unit mixer are combined by the third combiner. Output of the second combiner and output of the third combiner are combined by the first combiner. The output of the third unit mixer is input to the third combiner with the polarity being determined.

Mixer

A first switch is connected in parallel with a circuit element. A second switch is connected in series with a parallel circuit constituted by the circuit element and the first switch. The first switch and the second switch alternately perform on-off operation.

Switching circuit and variable attenuator

An image rejection mixer includes a delay circuit for delaying one of first signals divided by a distribution circuit and a second signal provided to a second mixing circuit by the same delay amount d, or delaying the other one of the first signals divided by the distribution circuit and the second signal provided to a first mixing circuit by the same delay amount d.

Image rejection mixer and communication circuit

One inductor and another inductor are magnetically coupled to each other. A variable current source controls the current flowing in the one inductor. By controlling the current flowing in the one inductor, the inductance value of the other inductor is made variable.

Variable inductor circuit

A mixer includes: a VGA () configured to amplify one of divided two portions of an input signal at a gain of cos &#x3b8;; a VGA () configured to amplify another one of the divided two portions of the input signal at a gain of sin &#x3b8;; an IQ generator () configured to input an LO wave, and output an LO wave in phase with the input LO wave and an LO wave having a phase difference of 90&#xb0; with respect to the input LO wave; a mixer () configured to input the signal output from the VGA () and the LO wave which is output from the IQ generator (), to output an RF signal; a second mixer () configured to input the signal from the VGA () and the LO wave which is output from the IQ generator, to output an RF signal; and a combiner ().

An NMOS transistor performs electrical conduction or cut-off between a drain and a source by controlling a potential at a gate. A resistive element is connected between a back gate of the NMOS transistor and a high-frequency ground. A first switching circuit is disposed in parallel with the resistive element between the back gate and the high-frequency ground and causes a short circuit between the back gate and the high-frequency ground upon cut-off.

High-frequency switch

A phase-frequency comparator compares a reference signal with an output signal from a variable frequency divider, and outputs an up signal of frequency and a down signal of frequency depending on results of the comparison. An AND circuit performs an AND operation between the up signal and the down signal, and outputs a result of the operation as a retiming si al CLKretime. A flip-flop circuit holds an output signal from a frequency control circuit at timing of the output signal from the AND circuit, and outputs the held output signal. At &#x394;&#x3a3; modulator determines a division ratio for the variable frequency divider on the basis of the output from the flip-flop circuit.

PLL circuit

A phase-locked loop circuit includes: a division ratio control circuit controlling a division ratio of an output signal of a variable frequency divider on the basis of an addition signal of a negative feedback signal and a division ratio setting signal indicating the division ratio, in synchronization with a divided signal output from the variable frequency divider; a first phase detection circuit calculating a first phase detection signal indicating a phase of an output signal of a signal output circuit; a second phase detection circuit calculating a second phase detection signal indicating a phase of the output signal of a case where it is assumed that the division ratio control circuit controls the division ratio of the output signal of the variable frequency divider in synchronization with the reference signal; and a shift circuit generating a negative feedback signal from a difference between the first phase detection signal and the second phase detection signal, and outputting an addition signal of the generated negative feedback signal and the division ratio setting signal to the division ratio control circuit.

Phase-locked loop circuit

A first pulse selector outputs an output signal of a variable frequency divider to phase frequency detectors in a time division manner. A second pulse selector outputs a reference signal from a reference signal source to the phase frequency detectors in a time division manner. Outputs of the phase frequency detectors are provided, respectively, for multiple disposed charge pump circuits.

An IQ signal source () includes: a Q-VCO () having a first VCO () and a second VCO (), the IQ signal source () outputting an I signal and a Q signal by electrically coupling the first VCO () and the second VCO () with each other; a first PLL () for comparing a frequency of the I signal or the Q signal with a frequency of a reference signal input from the outside of the IQ signal source () and outputting a voltage depending on a result of the comparison; and a second PLL () for detecting an IQ phase difference and outputting a voltage depending on the IQ phase difference. The IQ phase difference converges to 90 degrees in dependence on the output voltage of the first PLL () and the output voltage of the second PLL ().

IQ signal source

A local oscillator of the present invention includes: a frequency generator for outputting first and second sinusoidal signals having the same frequency but mutually different phases; a phase detector for outputting either a positive or a negative voltage depending on whether a phase difference between the first and second sinusoidal signals output from the frequency generator is greater than a reference phase difference; and a comparator for outputting a comparison result between a voltage output from the phase detector and a reference voltage, or a comparison result between the voltage output from the phase detector and a voltage obtained by inverting the polarity of the voltage, in which the frequency generator controls the phase of the first sinusoidal signal so that the phase difference approaches the reference phase difference by using the comparison result output from the comparator, enabling generating IQ signals having higher phase accuracy than conventional local oscillators.

Local oscillator

A first transistor (), a second transistor (), a third transistor () and a fourth transistor () are provided. A first transistor () amplifies a first I signal Vinputted from a first input terminal (). A second transistor () amplifies a first Q signal Vinputted from a second input terminal (). A third transistor () amplifies a second I signal Vwhen the second I signal Vis inputted from a third input terminal (), the second I signal Vforming a differential signal with the first I signal V. A fourth transistor () amplifies a second Q signal Vwhen the second Q signal Vis inputted from a fourth input terminal (), the second Q signal Vforming a differential signal with the first Q signal V.

Polyphase filter

A lock detector () detects an unlocked state from an output of a phase frequency comparator (). A counter () counts a reference signal, in a case where an unlocked state is detected by the lock detector (). A parameter controlling circuit () acquires the count value of the counter (), and controls switching on and off of a switch () for a D/A converter () that generates a signal to be added to an output of a loop filter (), and the output voltage of the D/A converter () so that the count value of the counter () falls within a set value.

Growing community of inventors

Tokyo, Japan

Mitsuhiro Shimozawa