Yamaha Corporation

Mitsuhiro Onoda

Ryota Hirose

A register stores the earliest time (IRL) at which a packet can be subsequently transmitted from a transmitting device in order to obey an allowable bandwidth given to the transmitting device, the earliest time (RL-to n) at which the packet of each class can be transmitted in order to obey the allowable bandwidth of the class, and a final time (RG-to n) at which the packet of each class is to be subsequently transmitted in order to maintain the guarantee bandwidth of the class. When a packet transmittable timing is reached, the packet of a class m which the final time (RG-to n) approaches is transmitted preferentially from the classes in which a current time reaches the earliest time (RL-to n). When the transmission of a packet is started, the next earliest time (IRL), earliest time (RL-m) of the class m and final time (RG-m) is determined based on the data volume of the packet.

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Hamamatsu, Japan

Mitsuhiro Onoda